MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1421

Manufacturer Part Number

BOARD DEV SYSTEM MPC8536E

Manufacturer

Freescale Semiconductor

PowerQUICC III™r

Board, Software and Documentation

Processor Series

Data Bus Width

Maximum Clock Frequency

Operating Supply Voltage

- 0.3 V to + 1.21 V

Maximum Operating Temperature

Data Ram Size

Interface Type

Program Memory Type

DDR2, DDR3, SDRAM

Program Memory Size

Digital Ic Case Style

Supply Voltage Range

0.95V To 1.05V

Rohs Compliant

For Use With/related Products

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

The scheduling cases are:

Freescale Semiconductor

Periodic Schedule

Case 1: The normal scheduling case is where the entire split transaction is completely bounded by

a frame (H-Frame in this case).

Case 2a through Case 2c: The USB 2.0 hub pipeline rules states clearly, when and how many

complete-splits must be scheduled to account for earliest to latest execution on the full/low-speed

link. The complete-splits may span the H-Frame boundary when the start-split is in micro-frame 4

or later. When this occurs, the H-Frame to B-Frame alignment requires that the queue head be

reachable from consecutive periodic frame list locations. System software cannot build an efficient

schedule that satisfies this requirement unless it uses FSTNs.

layout of the periodic schedule.

HS/FS/LS Bus

End of Frame

Figure 21-52. Split Transaction, Interrupt Scheduling Boundary Conditions

MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1

Figure 21-53

Universal Serial Bus Interfaces

illustrates the general