MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 813

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.5.3.3.8
RQFPR (see
filer table. The table entries are described in greater detail in
word accessed through RQFPR is defined by the current value of RQFAR.
describe the fields of the RQFPR register according to property ID.
Freescale Semiconductor
Offset eTSEC1:0x2_433C;
Reset
Reset
25–26
28–31
Bit
27
Offset eTSEC1:0x2_433C; eTSEC3:0x2_633C
Reset
W
W
R
R
eTSEC3:0x2_633C
W
R
EBC
16
Name
0
CMP
PID
0
—
Figure
Figure 14-31. Receive Queue Filer Table Property IDs 0, 2–15 Register Definition
VLN
17
Receive Queue Filer Table Property Register (RQFPR)
Comparison operation to perform on the RQPROP entry at this index when PID > 0. The property value
extracted by the frame parser is masked by the 32-bit mask_register prior to comparison against RQPROP.
However, the property value is not permanently altered by the value in mask_register . By default,
mask_register is initialized to 0xFFFF_FFFF before each frame is processed.
In the case where PID = 0, CMP is interpreted as follows:
00/01 Filer mask_register is set to all 32 bits of RQPROP, and this entry always matches .
10/11 Filer mask_register is set to all 32 bits of RQPROP, and this entry always fails to match .
In the case where PID > 0, CMP is interpreted as follows (& is bit-wise AND operator):
00 property [PID] & mask_register = RQPROP
01 property [PID] & mask_register >= RQPROP
10 property [PID] & mask_register != RQPROP
11 property [PID] & mask_register < RQPROP
Reserved, should be written with zero.
Property identifier. The value in the RQPROP entry at this index is interpreted according to PID (see
Table
Figure 14-32. Receive Queue Filer Table Property ID1 Register Definition
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
CFI
14-31) is accessed to read or write the RQPROP words in entries of the receive queue
14-36).
18
JUM
19
Table 14-35. RQFCR Field Descriptions (continued)
IPF
20
FIF
21
IP4
22
—
IP6
23
All zeros
All zeros
(undefined)
RQPROP
Description
ICC
24
Section 14.6.5.2, “Receive Queue Filer.”
ICV
25
TCP
Enhanced Three-Speed Ethernet Controllers
26
Figure 14-31
UDP
27
28
—
and
Access: Read/Write
Access: Read/Write
13
29
Figure 14-32
PER
AR
14
30
ARQ
EER
14-65
The
15
31
31