MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1572

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Reads or writes from eTSEC 1 or
eTSEC3
Reads or writes from high speed
interfaces (PCI and PEX2)
Reads or writes from high speed
interfaces (PCI and PEX1–3)
Reads or writes from DMA
Reads or writes from Security
Row open table hits for reads or writes
from core (data and inst)
Row open table hits for reads or writes
from eTSEC 1 or eTSEC3
Row open table hits for reads or writes
from high speed interfaces (PCI and
PEX2)
Row open table hits for reads or writes
from high speed interfaces (PCI and
PEX1–3)
Row open table hits for reads or writes
from DMA
Row open table hits for reads or writes
from Security
Channel 0 read request
Channel 1 read request
Channel 2 read request
Channel 3 read request
Channel 0 write request
Channel 1 write request
Channel 2 write request
Channel 3 write request
Channel 0 descriptor request
Channel 1 descriptor request
Channel 2 descriptor request
Channel 3 descriptor request
Channel 0 read DW or less
Channel 1 read DW or less
Device Performance Monitor
24-18
Event Counted
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 24-10. Performance Monitor Events (continued)
C1:68 and C5:117 DMA channel 0 read double word valid
C2:71 and C6:122 DMA channel 1 read double word valid
Number
C5:105
C6:108
C7:105
C8:105
Ref:14
C3:65
C3:66
C4:67
C5:66
C6:69
C6:65
C6:66
C7:65
C8:66
C7:68
C1:66
C2:69
C3:68
C4:70
C1:67
C2:70
C3:69
C4:71
DMA Controller Events
—
—
—
—
—
—
—
—
—
—
—
DMA channel 0 read request active in the system
DMA channel 1 read request active in the system
DMA channel 2 read request active in the system
DMA channel 3 read request active in the system
DMA channel 0 write request active in the system
DMA channel 1 write request active in the system
DMA channel 2 write request active in the system
DMA channel 3 write request active in the system
DMA channel 0 descriptor request active in the system
DMA channel 1 descriptor request active in the system
DMA channel 2 descriptor request active in the system
DMA channel 3 descriptor request active in the system
Description of Event Counted
Freescale Semiconductor