MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 482

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Security Engine (SEC) 3.0
10-52
12–14
20–23
24–31
Table 10-19. Field Names in Interrupt Enable, Interrupt Status, and Interrupt Clear Registers (continued)
Bits
10
11
15
9
Err and Dn
(CHN_1 to
DO_CNT
DF_CNT
channels
Overflow
DI_CNT
CHN_4)
bits for
Name
Done
ITO
—
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Descriptor Finished Count Rollover
0 No rollover.
1 The Descriptor Finished Counter rolled over to zero (see
Counter”).
Data In Count Rollover
0 No rollover.
1 The Data In Counter rolled over to zero (see
Data Out Count Rollover
0 No rollover.
1 The Data Out Counter rolled over to zero (see
Reserved
Internal Time Out
0 No internal time out
1 an internal time out was detected
Note: Internal time out is an indication that a channel or EU has failed to respond to a slave read or
Done Overflow (one bit for each channel—CH1 to CH4)
0 No done overflow
1 Done overflow error. Indicates that more than 15 Done interrupts were queued from the associated
Err
0 No error detected.
1 Error detected. Indicates that channel status register must be read to determine exact cause of the
Dn
0 Not DONE.
1 DONE bit indicates that the corresponding channel has completed a descriptor.
channel without a corresponding interrupt clear from the host.
error.
write within 16 cycles, which would only occur in an impending hang condition. Assertion of this
interrupt indicates the SEC controller has completed the transaction to avoid a hang—however
the ’completed’ transaction does not result in a successful read or write, and the interrupt
advises the system that the slave transaction was unsuccessful.
Description
Section 10.4.3.1.2, “Descriptor Finished
Section 10.4.3.1.2, “Descriptor Finished
Section 10.4.3.1.2, “Descriptor Finished
Freescale Semiconductor
Counter”).
Counter”).