MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1573

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Channel 2 read DW or less
Channel 3 read DW or less
Channel 0 write DW or less
Channel 1 write DW or less
Channel 2 write DW or less
Channel 3 write DW or less
ECM request wait core
ECM request wait I
ECM request wait PEX1–3/DMA
ECM request wait eTSEC1/3
ECM request wait
USB1–3/eSDHC/SATA1–2
ECM dispatch
ECM dispatch from USB2
ECM dispatch from eTSEC1
ECM dispatch from eTSEC3
ECM dispatch from SATA1
ECM dispatch from SATA2
ECM dispatch from eSDHC
ECM dispatch from PCI
ECM dispatch from PEX2
ECM dispatch from PEX1
ECM dispatch from PEX3
ECM dispatch from DMA
ECM dispatch from Security
ECM dispatch from USB1
ECM dispatch from USB3 or boot
sequencer
ECM dispatch to DDR
ECM dispatch to L2
ECM dispatch to SRAM
ECM dispatch to eLBC
Freescale Semiconductor
Event Counted
2
C/Security
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 24-10. Performance Monitor Events (continued)
C3:70 and C7:118 DMA channel 2 read double word valid
C4:72 and C8:116 DMA channel 3 read double word valid
e500 Coherency Module (ECM) Events
Number
Ref:15
C1:69
C2:72
C3:71
C4:73
C8:77
C7:77
C5:80
C6:80
C4:84
C3:83
C4:85
C9:80
C8:99
C6:81
C7:80
C8:81
C7:94
C7:78
C9:81
C9:82
C5:83
C5:82
C6:82
C7:79
C3:80
C8:79
C9:83
DMA channel 0 write double word valid
DMA channel 1 write double word valid
DMA channel 2 write double word valid
DMA channel 3 write double word valid
Asserted for every cycle core request occurs
Asserted for every cycle I
Asserted for every cycle PEX1-3/DMA request occurs
Asserted for every cycle eTSEC1/3 request occurs
Asserted for every cycle USB1–3/eSDHC/SATA1–2 request occurs
ECM dispatch (includes address only’s)
Note: All ECM dispatch events are for committed dispatches
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ECM dispatch to DDR (excludes address only)
—
—
—
Description of Event Counted
2
C/Security request occurs
Device Performance Monitor
24-19