MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 999

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DMA Controller
15.3.1.3
Current Link Descriptor Address Registers (CLNDAR n and ECLNDAR n )
Current link descriptor address registers contain the address of the current link descriptor. In basic chaining
mode, shown in
Figure
15-6, software must initialize these registers to point to the first link descriptors in
memory.
Software initializes CLNDAR n with 1st link descriptor
1st link descriptor is processed
Current link descriptor <- Next link descriptor
Is
N
Y
NLNDAR n [EOLND]
set?
Last link descriptor has been processed
Is
Y
Extended Chaining
enabled?
N
Is
Y
NLSDAR n [EOLSD]
set?
N
Done — DMA halts
CLSDAR n <- NLSDAR n
Figure 15-6. Basic Chaining Mode Flow Chart
After the current descriptor is processed, the current link descriptor address register is loaded from the next
link descriptor address registers and NLNDARn[EOLND] in the next link descriptor address register is
examined. If EOLND is zero, the DMA controller reads in the new current link descriptor for processing.
If EOLND is set, the last descriptor of the list was just completed. If extended chaining mode is not
enabled, all DMA transfers are complete and the DMA controller halts.
If extended chaining mode is enabled, the DMA controller examines the state of NLSDARn[EOLSD] in
the next list descriptor address register. If EOLSD is clear, the controller loads the contents of the next list
descriptor address register into the current list descriptor address register and reads the new list descriptor
from memory. If EOLSD is set, all DMA transfers are complete and the DMA controller halts.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Freescale Semiconductor
15-13