MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1022

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DMA Controller
Figure 15-26
Figure 15-27
15.4.5
This section addresses some of the limitations and restrictions of the DMA controller and is intended to
help software maximize the DMA performance and avoid DMA programming errors.
The limitations of the DMA controller are the following:
The DMA controller restrictions are as follows:
15-36
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Due to the limited number of buffers that the DMA controller can use, stride sizes less than 64 bytes
should be avoided. Maximum utilization is obtained from strides greater than or equal to 256 bytes.
However, small stride sizes can be used for scatter-gather functions.
Coherent reads or writes are broken up into cache line accesses in the DMA.
All interface capabilities from where descriptors are being fetched must support read sizes of 32
bytes or greater.
If MRn[SAHE] is set, the source interface transfer size capability must be greater than or equal to
MRn[SAHTS]. The source address must be aligned to a size specified by SAHTS.
Limitations and Restrictions
describes the format of the list descriptors.
describes the format of the link descriptors.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Offset
Offset
0x00
0x04
0x08
0x0C
0x10
0x14
0x18
0x1C
0x00
0x04
0x08
0x0C
0x10
0x14
0x18
0x1C
Figure 15-27. Link Descriptor Format
Figure 15-26. List Descriptor Format
First Link Descriptor Extended Address
Next Link Descriptor Extended Address
Next List Descriptor Extended Address
Next Link Descriptor Address
First Link Descriptor Address
Next List Descriptor Address
Destination Attributes
Destination Address
Destination Stride
Source Attributes
Source Address
Source Stride
Reserved
Reserved
Byte Count
Reserved
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