MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1187

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

17.3.10.13 LTSSM State Status Register—0x404
The PCI Express link training and status state machine (LTSSM) state status register, shown in
Figure
debugging link training failures.
Offset 0x404
The fields of the PCI Express LTSSM state status register are described in
Table 17-111
Freescale Semiconductor
Reset
Status Code
W
R
31–7
Bits
6–0
(Hex)
31
17-114, provides detailed information about link training status. This register is useful for
0C
0D
0A
0B
0E
0F
00
01
02
03
04
05
06
07
08
09
Status code Status code. See
Name
provides the encodings for the status code field of the PEX_LTSSM_STAT register.
Figure 17-114. PCI Express LTSSM State Status Register (PEX_LTSSM_STAT)
—
Detect quiet
Detect active (0)
Detect active (1)
Detect active (2)
Polling active (0)
Polling active (1)
Polling config (0)
Polling config (1)
Polling compliance
Configuration link width start (0)
Configuration link width start (1)
Configuration link width accept (0)
Configuration link width accept (1)
Configuration lane number wait (0)
Configuration lane number wait (1)
Configuration lane number wait (2)
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Reserved
LTSSM State Description
Table 17-110. PEX_LTSSM_STAT Field Descriptions
Table 17-111. PEX_LTSSM_STAT Status Codes
Table 17-111
—
for encodings.
All zeros
Status Code
Description
(Hex)
2C
2D
27
28
29
2A
2B
2E
2F
30
31
32
33
34
35
36
TX L0s FTS; RX L0s FTS
L0 to L1 (0)
L0 to L1 (1)
L1 entry
L1 idle (0)
L1 idle (1)
L0 to L2 (0)
L0 to L2 (1)
L2 entry
L2 idle (0)
L2 idle (1)
Recovery lock (0)
Recovery lock (1)
Recovery lock (2)
Recovery cfg (0)
Recovery cfg (1)
LTSSM State Description
Table
PCI Express Interface Controller
17-110.
7
6
Status Code
Access: Read only
17-91
0