MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 965

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 14-178
Table 14-179
Freescale Semiconductor
ECGTX_CLK125
eTSEC Signals
Set up the MII Mgmt for a read cycle to TBI’s Control register (write the TBI address and Register address),
MDIO
MDC
set source clock divide by 14 for example to insure that MDC clock speed is not greater than 2.5 MHz
Sum
describes the shared signals for the TBI interface.
describes the register initializations required to configure the eTSEC in TBI mode.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
I/O
I/O
O
MACSTNADDR2[0110_0000_0000_0010_0000_0000_0000_0000]
MACSTNADDR1[0100_0011_0110_0101_1000_0111_1000_1100]
I
MIIMIND ---> [0000_0000_0000_0000_0000_0000_0000_0000]
MACCFG1[1000_0000_0000_0000_0000_0000_0000_0000]
MACCFG1[0000_0000_0000_0000_0000_0000_0000_0000]
MACCFG2[0000_0000_0000_0000_0111_0010_0000_0101]
The control register (CR) is at offset address 0x0 from TBIPA.
Table 14-179. TBI Mode Register Initialization Steps
MIIMCFG[0000_0000_0000_0000_0000_0000_0000_0101]
MIIMADD[0000_0000_0000_0000_0001_0000_0000_0000]
ECNTRL[0000_0000_0000_0000_0001_0000_0000_0000]
Read MII Mgmt Indicator register and check for Busy = 0,
TBIPA[0000_0000_0000_0000_0000_0000_0001_0000]
Signals
This indicates that the eTSEC MII Mgmt bus is idle.
No. of
1
1
1
3
(This example has Statistics Enable = 1)
Table 14-178. Shared TBI Signals
Assign a Physical address to the TBI,
Setup the MII Mgmt clock speed,
to 02608C:876543, for example.
to 02608C:876543, for example.
(I/F Mode = 2, Full Duplex = 1)
Initialize MAC Station Address
Initialize MAC Station Address
set to 16, for example.
GTX_CLK125
GMII Signals
Initialize MACCFG2,
Initialize ECNTRL,
Clear Soft_Reset,
Set Soft_Reset,
MDIO
MDC
Sum
I/O
I/O
O
I
Signals
No. of
Enhanced Three-Speed Ethernet Controllers
1
1
1
3
Management interface clock
Management interface I/O
Reference clock
Function
14-217