MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1297

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Freescale Semiconductor
AC12E
DMAE
DEBE
Offset: 0x030 (IRQSTAT)
Field
DCE
Reset
Reset
0–2
4–6
10
3
7
8
9
W
W
R
R
16
Reserved
DMA error. Occurs when internal DMA transfer failed. This bit is set when some error occurs in the data transfer.
The value in the DMA system address register is the next fetch address where the error occurs. Since any error
corrupts the entire data block, the host driver should restart the transfer from the corrupted block boundary. The
address of the block boundary can be calculated from the current DS_ADDR value or the remaining number of
blocks and the block size.
0 No Error
1 Error
Reserved
Auto CMD12 error. Occurs when one of the bits in AUTOC12ERR is set. This bit is also set when Auto CMD12 is
not executed due to a previous command error.
0 No Error
1 Error
Reserved
Data end bit error. Occurs when detecting 0 at the end bit position of read data on the SDHC_DAT line or at the end
bit position of the CRC.
0 No Error
1 Error
Note: When DEBE and CINT are set, the software should ignore DEBE. But, it must not ignore the other status bits.
Data CRC error. Occurs when detecting CRC error when transferring read data on the SDHC_DAT line or when
detecting the write CRC status having a value other than 0b010.
0 No Error
1 Error
0
—
The software should also clear this bit by writing 1 to it. It is highly recommended to clear this bit before the
next transfer.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
2
DMAE
w1c
3
—
Figure 20-12. Interrupt Status Register (IRQSTAT)
Table 20-14. IRQSTAT Field Descriptions
4
—
22
6
AC12E
CINT
w1c
w1c
23
7
Description
All zeros
All zeros
CRM CINS BRR
w1c
—
24
8
DEBE DCE DTOE
w1c
w1c
25
9
w1c
w1c
10
26
Enhanced Secure Digital Host Controller
BWR DINT
w1c
w1c
11
27
w1c
w1c
CIE
12
28
CEBE
BGE
w1c
w1c
13
29
CCE
w1c
w1c
Access: w1c
TC
14
30
CTOE
20-23
w1c
w1c
CC
15
31