MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 499

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Context for ECB Mode
ECB does not use any context registers.
Context for CBC, CBC-RBP, OFB, and CFB128 Cipher Modes
In CBC, CBC-RBP, OFB, and CFB128 cipher modes, the first two context data registers allow the host to
read/write the contents of the initialization vector (IV) as follows:
The IV must be written prior to the message data. If the IV registers are written during message processing,
or the mode is not set, a context error is generated.
The IV registers may only be read after processing has completed, as indicated by the assertion of the done
interrupt (DI) bit in the AESU status register (see
registers are read prior to the assertion of DI, then an early read error is generated.
Context for Counter (CTR) Cipher Mode
In counter cipher mode, a random 128-bit initial counter value is incremented modulo 2
processed. The running counter is encrypted and XORed with the plaintext to derive the ciphertext, or with
the ciphertext to recover the plaintext. The modulus exponent M can be set between 8 and 128, in multiples
of 8.
As shown in
register 7 holds the modulus exponent M .
Freescale Semiconductor
Notes:
Context Registers 8 through 12 are not used for these modes
* Must be written at start of new message, except if zero
— don’t care
Context Register
•
•
(byte address)
1 (0x34100)
2 (0x34108)
3 (0x34110)
4 (0x34118)
5 (0x34120)
6 (0x34128)
7 (0x34130)
Context register 1 holds the least significant bytes of the initialization vector (bytes 1–8).
Context register 2 holds the most significant bytes of the initialization vector (bytes 9–16).
Table
10-29, in CTR mode context registers 5–6 hold the initial counter value, and context
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 10-29. AESU Context Registers for Confidentiality Modes
ECB
—
—
—
—
CBC / CBC-RBP /
OFB / CFB128
IV*
—
—
—
Confidentiality-only Cipher Mode
Section 10.7.1.6, “AESU Status
Counter Modulus
Initial Counter
Exponent*
Value*
CTR
0
0
sector size*
XTS
—
—
—
I*
Register”). If the IV
Security Engine (SEC) 3.0
Counter Modulus*
M
Initial Counter
with each block
Value*
SRT
—
—
—
10-69