MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1387

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

21.5.5.3
The third DWord of a queue element transfer descriptor contains most of the information the host
controller requires to execute a USB transaction (the remaining endpoint-addressing information is
specified in the queue head). Note that some of the field descriptions in
defined in the queue head. See
Freescale Semiconductor
30–16 Total Bytes
14–12
Bits
31
15
to Transfer
C_Page
Name
ioc
dt
qTD Token
Data toggle. This is the data toggle sequence bit. The use of this bit depends on the setting of the Data
Toggle Control bit in the queue head.
Total bytes to transfer. This field specifies the total number of bytes to be moved with this transfer
descriptor. This field is decremented by the number of bytes actually moved during the transaction, only
on the successful completion of the transaction. The maximum value software may store in this field is
5
field is zero when the host controller fetches this transfer descriptor (and the active bit is set), the host
controller executes a zero-length transaction and retires the transfer descriptor. It is not a requirement for
OUT transfers that total bytes to transfer be an even multiple of QH[Maximum Packet Length]. If software
builds such a transfer descriptor for an OUT transfer, the last transaction will always be less than
QH[Maximum Packet Length]. Although it is possible to create a transfer up to 20K this assumes the page
is 0. When the offset cannot be predetermined, crossing past the 5th page can be guaranteed by limiting
the total bytes to 16K. Therefore, the maximum recommended transfer is 16K (0x4000).
Interrupt on complete. If this bit is set, the host controller should issue an interrupt at the next interrupt
threshold when this qTD is completed.
Current rage. This field is used as an index into the qTD buffer pointer list. Valid values are in the range
0x0 to 0x4. The host controller is not required to write this field back when the qTD is retired.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
4K (0x5000). This is the maximum number of bytes 5 page pointers can access. If the value of this
Section 21.5.6, “Queue Head,”
Table 21-53. qTD Token (DWord 2)
Description
for more information on these fields.
Table 21-53
Universal Serial Bus Interfaces
reference fields are
21-53