MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1112

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PCI Express Interface Controller
17.3.3.3
The PCI Express PME and message interrupt enable register, shown in
detection of a message or a PME event to generate an interrupt, provided that the corresponding bit in the
PCI Express PME and message detect register is set.
17-16
23–24
Bits
21
22
25
26
27
28
29
30
31
AIOND
PIOND
AIOFD
PIOFD
HRDD
Name
LDDD
ABPD
AIBD
PIBD
—
PCI Express PME and Message Interrupt Enable Register
(PEX_PME_MES_IER)
Hot reset detected disable. When set, this bit disables the setting of PEX_PME_MES_DR[HRD] bit.
1 Disable hot reset state detection
0 Enable hot reset state detection
Link down detected disable. When set, this bit disables the setting of PEX_PME_MES_DR[LDD] bit.
1 Disable link down state detection
0 Enable link down state detection
Reserved
Attention indicator on disable. When set, this bit disables the setting of PEX_PME_MES_DR[AION] bit.
1 Disable attention indicator on message detection
0 Enable attention indicator on message detection
Attention indicator blink disable. When set, this bit disables the setting of PEX_PME_MES_DR[AIB] bit.
1 Disable attention indicator blink message detection
0 Enable attention indicator blink message detection
Attention indicator off disable. When set, this bit disables the setting of PEX_PME_MES_DR[AIOF] bit.
1 Disable attention indicator off message detection
0 Enable attention indicator off message detection
Power indicator on disable. When set, this bit disables the setting of PEX_PME_MES_DR[PION] bit.
1 Disable power indicator on message detection
0 Enable power indicator on message detection
Power indicator blink disable. When set, this bit disables the setting of PEX_PME_MES_DR[PIB] bit.
1 Disable power indicator blink message detection
0 Enable power indicator blink message detection
Power indicator off disable. When set, this bit disables the setting of PEX_PME_MES_DR[PIOF] bit.
1 Disable power indicator off message detection
0 Enable power indicator off message detection
Attention button pressed disable. When set, this bit disables the setting of PEX_PME_MES_DR[ABP] bit.
1 Disable attention button press message detection
0 Enable attention button press message detection
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 17-10. PEX_PME_MES_DISR Field Descriptions (continued)
Description
Figure
17-9, allows for the
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