MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 439

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The DEU operates by permuting 64-bit data blocks with a shared 56-bit key and an initialization vector
(IV). The SEC supports four modes of operation:
For more information about the unit’s operation, refer to
Execution Unit (DEU).”
10.1.4.3
The AESU is used to accelerate bulk data encryption/decryption in compliance with the Advanced
Encryption Standard algorithm Rijndael specified by NIST standard FIPS-197. The AESU executes on
128 bit blocks with a choice of key sizes: 128, 192, or 256 bits.
AES is a symmetric key algorithm, meaning the sender and receiver use the same key for encryption and
decryption. The session key and IV are supplied to the AESU module prior to encryption. The processor
supplies data to the module that is processed as 128 bit input.
AESU implements the following confidentiality modes from NIST Recommendation 800-38A:
AESU also implements other NIST recommended modes providing authentication (two of which also
provide confidentiality):
AESU modes also implement the following modes not sanctioned by NIST:
In all modes supporting authentication, the AESU hashes data to produce an integrity check vector (ICV).
If a reference ICV is supplied to the AESU, it can do a bitwise check of the reference ICV against the one
computed by the AESU.
For more information about the unit’s operation, refer to
Execution Unit (AESU).”
Freescale Semiconductor
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Electronic Code Book (ECB)
Cipher Clock Chaining (CBC)
64-bit Cipher Feedback Mode (CFB-64)
64-bit Output Feedback Mode (OFB-64).
Electronic Codebook mode (ECB)
Cipher Block Chaining mode (CBC)
Output Feedback mode (OFB)
128-bit Cipher Feedback mode (CFB-128)
Counter mode (CTR)
Counter with CBC-MAC (CCM) per NIST recommendation 800-38C
Galois Counter Mode (GCM) per NIST draft recommendation 800-38D
Cipher-based MAC (CMAC) per NIST recommendation 800-38B.
Note that CMAC is identical to OMAC1.
XTS as specified by IEEE P1619 Draft 11
CBC-RBP
XCBC-MAC as specified by IETF RFC-3566
Advanced Encryption Standard Execution Unit (AESU)
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Section 10.7.1, “Advanced Encryption Standard
Section 10.7.4, “Data Encryption Standard
Security Engine (SEC) 3.0
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