MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1598

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Debug Features and Watchpoint Facility
Table 25-14
25-16
14–15 MODE Trace mode. Specifies one of two trace modes.
16–20
8–13
Bits
0
1
2
3
4
5
6
7
NECEN Not equal context enable. Qualifies the matching of current context with programmed context as a trace buffer
SIDEN Source ID enable
TIDEN Target ID enable
Name
ECEN Equal context enable. Qualifies the matching of current context with programmed context as a trace buffer event
HALT Halt causes the trace buffer to stop tracing immediately. TBSR[ACT] remains set when this bit is set.
AMD
TMD
EN
—
—
describes the TBCR0 fields.
Enable
0 The trace buffer facility is disabled.
1 The trace buffer facility is enabled.
Address match disable
0 The address match is used to qualify a trace buffer event.
1 The address match is ignored when detecting a trace buffer event.
Transaction match disable
0 The transaction type match is used to qualify a trace buffer event.
1 The transaction type match is ignored when detecting a trace buffer event.
criterion, as written in the context registers described in
0 Current context match does not affect trace buffer event detection
1 Trace buffer events are qualified by comparing current context with the programmed context event value.
Note: ECEN and NECEN must not be enabled in the same run. If both are set, watchpoint events are inhibited
event criterion, as written in the context registers described in
0 The failure of a current context match does not affect trace buffer event detection
1 trace buffer events are qualified with NOT getting a current context compare with the programmed context
Note: ECEN and NECEN must not be enabled in the same run. If both are set, watchpoint events are inhibited
0 Trace buffer events ignore the programmed source ID value.
1 Trace buffer events are qualified by comparison with the programmed SID event value.
0 Trace buffer events ignore the programmed TID event value.
1 Trace buffer events are qualified by comparison with the programmed TID event value. This comparison only
Reserved
00 Trace every valid transaction
01 Reserved
10 Trace only cycles in which a trace event is detected. Note that if EN and other TBCR0 fields are not properly
11 Reserved
Reserved
event value.
applies when the ECM is selected for tracing (TBCR1[IFSEL] is all zeros).
programmed to specify a traceable event, tracing occurs for every valid address.
(never occur).
(never occur).
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 25-14. TBCR0 Field Descriptions
Description
Section 25.3.3, “Context ID Registers.”
Section 25.3.3, “Context ID Registers.”
Freescale Semiconductor