MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 586

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Security Engine (SEC) 3.0
Most of the registers described here would not normally be accessed by the host. They are documented
here mainly for debug purposes. In typical operation, the RNGU is used through channel-controlled
access, which means that most reads and writes of RNGU registers are directed by the SEC channels.
Driver software would perform host-controlled register accesses only on a few registers for initial
configuration and error handling.
10.7.8.1
The RNGU Mode Register is a writable location but all mode bits are currently reserved. It is documented
for the sake of consistency with the other EUs. The RNGU mode register is shown in
Offset 0x3_A000
10.7.8.2
The RNGU data size register is used to tell the RNGU to begin generating random data. The actual
contents of the data size register does not affect the operation of the RNGU. After a reset and prior to the
first write of data size, the RNGU builds entropy without pushing data onto the FIFO. Once the data size
register is written, the RNGU begins pushing data onto the FIFO. One dword (64 bits) of data is pushed
onto the FIFO every 112 cycles until the FIFO is full. The RNGU then attempts to keep the FIFO full.
Offset 0x3_A010
10.7.8.3
This register, shown in
Table 10-72
10-156
Reset
Reset
Offset 0x3_A018
Reset
W
W
W
R
R
R
0
0
0
describes RNGU reset control register fields.
RNGU Mode Register
RNGU Data Size Register
RNGU Reset Control Register
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Figure
10-105, contains three reset options specific to the RNGU.
Figure 10-105. RNGU Reset Control Register
Figure 10-104. RNGU Data Size Register
Figure 10-103. RNGU Mode Register
—
All zeros
All zeros
All zeros
—
—
Freescale Semiconductor
Figure
Access: Read/Write
Access: Read/Write
Access: Read/Write
10-103.
60 61 62 63
RI MI SR
63
63