MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 463

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Typical operations performed by a channel to process a descriptor are:
10.4.1.2
All channels share a set of common resources, including the EUs and the SEC’s bus master interface
(managed by the SEC controller). When multiple channels are used in parallel, arbitration may be required
to determine which channel is serviced. The different arbitration schemes are described in
“Arbitration Algorithms.”
Generally speaking, no arbitration for use of the controller/bus master interface is required. The channels
within the polychannel execute one at a time, so individual channels do not experience contention when
requests to the controller. In effect, when a channel wins arbitration for use of the polychannel, it wins use
of the controller as well.
The same is not true of EUs. Once the controller has assigned an EU to a channel, that channel owns the
EU for the duration of descriptor processing. The maximum amount of data that can be processed by a
single descriptor is 64 Kbytes, which prevents a channel from owning an EU for an unbounded length of
time.
Freescale Semiconductor
1. Analyze the descriptor header to determine the cryptographic services required, and arbitrate for
2. Set the mode register in each reserved EU(s) for the required EU function.
3. Fetch “parcels” (up to 64K–1 bytes long) from system memory using pointers from the descriptor
4. Take data accumulated in the EU output FIFO and write it to system memory using pointers from
5. If the data size is greater than EU FIFO size, continue fetching input data and writing output data
6. After writing the last input data to each EU’s input FIFO, write to the end of message register in
7. Wait for EU(s) to complete processing of text data.
8. Unload final results from output FIFOs and context registers and write them to external memory
9. Reset and release the EUs.
10. If enabled, then notify the host of descriptor completion (see
the appropriate EUs. If required EUs are already reserved by another channel, wait for the EUs to
be available. When available, reserve them.
buffer, and place them in either an EU input FIFO or EU registers, as appropriate. The term
“parcel” refers here to any input or output of an EU algorithm, such as a key, hash result, input
context, output context, or text data. “Context” refers to either an IV (initialization vector) or other
internal EU state that can be read out or loaded in. “Text data” refers to plaintext or ciphertext to
be operated on. Each parcel transfer may involve using link tables to gather input data that has been
split into multiple segments in system memory.
the descriptor buffer. This may again involve using link tables to scatter output data into multiple
segments in system memory.
to memory as needed.
the EU.
using pointers from the descriptor buffer. This may again involve using link tables to scatter output
data into multiple segments in system memory.
Notification”).
Channel Arbitration
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Section 10.4.1.3, “Channel Host
Security Engine (SEC) 3.0
Section 10.5.2,
10-33