MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 429

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

When the PIC is in mixed mode (GCR[M] = 1), the following guidelines are recommended:
In addition, the following initialization sequence is recommended:
Depending on the interrupt system configuration, the PIC may generate spurious interrupts to clear
interrupts latched during power-up. A spurious or non-spurious vector is returned for an interrupt
acknowledge cycle in this case. See the programming note below for the non-spurious case.
Freescale Semiconductor
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1. Write the vector, priority, and polarity values in each interrupt’s vector/priority register, leaving
2. Clear CTPR (CTPR = 0x0000_0000).
3. Program the PIC to mixed mode by setting GCR[M].
4. Clear the MSK bit in the vector/priority registers to be used.
5. Perform a software loop to clear all pending interrupts:
6. Set the processor core CTPR values to the desired values.
7. Read the MSIRs to clear any pending message signaled interrupts that may have been pending
8. Set MER to 0x0000_000F. See
All PIC registers must be located in a cache-inhibited, guarded area (configured through the core’s
MMU).
The PIC portion of the address map must be set up appropriately.
their MSK (mask) bit set. This is required only if interrupts are used.
— Load counter with FRR[NIRQ].
— While counter > 0, read IACK and write EOI to guarantee all the IPR and ISR bits are cleared.
before a soft reset.
information.
Because the default polarity/sense for external interrupts is edge-sensitive,
and edge-sensitive interrupts are not cleared until they are acknowledged, it
is possible for the PIC to store spurious edges detected during power-up as
pending external interrupts. If software permanently configures an external
interrupt source to be edge-sensitive, it may receive the vector for the
interrupt source and not a spurious interrupt vector when software clears the
mask bit. This can occur once for any edge-sensitive interrupt when its mask
bit is first cleared and the PIC is in mixed mode.
To avoid a false interrupt for this case, software can clear the IPR of these
spurious edge detections by first configuring the polarity/sense of external
interrupt sources to be level-sensitive: high-level if the input is a
positive-edge source and low-level if it is a negative-edge source (while the
mask bit remains set). After this is complete, configuring the external
interrupt source as edge-sensitive does not cause a false interrupt.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Section 9.3.5.2, “Message Enable Register
NOTE
Programmable Interrupt Controller (PIC)
(MER),” for more
9-59