MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 783

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.5.3.1.6
ECNTRL is a register writable by the user to reset, configure, and initialize the eTSEC. Note that the
FIFM, GMIIM, TBIM, RPM, and RMM fields are read-only, having been set after sampling signals at
power-on-reset.
Figure 14-7
Table 14-11
Freescale Semiconductor
Offset eTSEC1:0x2_4020;
Reset
Reset
Bits
30
31
0–15
Bits
16
17
W
W
R
R FIFM
eTSEC3:0x2_6020
16
0
PERRDIS
DPEDIS
CLRCNT Clear all statistics counters and carry registers.
Name
Name
describes the definition for the ECNTRL register.
FIFM
CLRCNT AUTOZ STEN
describes the fields of the ECNTRL register.
—
Ethernet Control Register (ECNTRL)
17
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Data parity error disable.
0 Allow eTSEC to report IEVENT[DPE] status.
1 Do not set IEVENT[DPE] if a parity error occurs in eTSEC’s FIFO or filer arrays.
Receive frame parse error disable.
0 Allow eTSEC to report IEVENT[PERR] status.
1 Do not set IEVENT[PERR] if a parse error occurs on a received frame.
Reserved
FIFO mode enable. If this bit is set, 8-bit FIFO interface mode is enabled. This bit can be pin configured
at reset to set or clear. See
0 Interface to external signals through the Ethernet MAC.
1 Interface to external signals through the 8-bit FIFO interface, bypassing the Ethernet MAC. Frame
0 Allow MIB counters to continue to increment and keep any overflow indicators.
1 Reset all MIB counters and CAR1 and CAR2.
This bit is self-resetting.
parsing in this mode automatically assumes that IP packets are being received and transmitted. See
FIFOCFG register for configuration of the FIFO interface.
18
Table 14-10. EDIS Field Descriptions (continued)
19
Figure 14-7. ECNTRL Register Definition
Table 14-11. ECNTRL Field Descriptions
20
Section 4.4.3, “Power-On Reset
—
All zeros
All zeros
—
24
Description
Description
GMIIM TBIM RPM
25
26
Configuration.”
Enhanced Three-Speed Ethernet Controllers
27
R100M
28
RMM SGMIIM
29
Access: Mixed
30
14-35
—
15
31