MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 723

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 13-40
Freescale Semiconductor
Reset
Reset
W
W
10–11
R
R
Bits
8–9
12
13
14
15
0
1
2
3
4
5
6
7
CST1 CST2 CST3 CST4 BST1 BST2 BST3 BST4
G3T1 G3T3
16
0
contains descriptions of the RAM word fields.
Name
CST1
CST2
CST3
CST4
BST1
BST2
BST3
BST4
G1T1
G1T3
G2T1
G2T3
G0H
G0L
17
1
G4T1/
DLT3
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
18
2
General purpose line 0 lower. Defines the state of LGPL0 during the bus clock quarter phases
1 and 2 (first half phase).
00 Value defined by M x MR[G0CL]
01 Reserved
10 0
11 1
General purpose line 0 higher. Defines the state of LGPL0 during the bus clock quarter phases
3 and 4 (second half phase).
00 Value defined by M x MR[G0CL]
01 Reserved
10 0
11 1
phases 1 and 2 (first half phase).
phases 3 and 4 (second half phase)
General purpose line 2 timing 1. Defines state (0 or 1) of LGPL2 during bus clock quarter
phases 1 and 2 (first half phase).
phases 3 and 4 (second half phase).
Chip select timing 1. Defines the state (0 or 1) of LCS n during bus clock quarter phase 1.
Chip select timing 2. Defines the state (0 or 1) of LCS n during bus clock quarter phase 2.
Chip select timing 3. Defines the state (0 or 1) of LCS n during bus clock quarter phase 3.
Chip select timing 4. Defines the state (0 or 1) of LCS n during bus clock quarter phase 4.
Byte select timing1. Defines the state (0 or 1) of LBS during bus clock quarter phase 1.
Byte select timing 2. Defines the state (0 or 1) of LBS during bus clock quarter phase 2.
Byte select timing 3. Defines the state (0 or 1) of LBS during bus clock quarter phase 3.
Byte select timing 4. Defines the state (0 or 1) of LBS during bus clock quarter phase 4.
General purpose line 1 timing 1. Defines the state (0 or 1) of LGPL1 during bus clock quarter
General purpose line 1 timing 3. Defines the state (0 or 1) of LGPL1 during bus clock quarter
General purpose line 2 timing 3. Defines the state (0 or 1) of LGPL2 during bus clock quarter
WAEN
G4T3/
19
3
G5T1 G5T3
Table 13-40. RAM Word Field Descriptions
20
4
Figure 13-66. RAM Word Fields
21
5
22
6
REDO
23
7
All zeros
All zeros
LOOP EXEN
Description
24
8
G0L
25
9
10
26
AMX
G0H
11
27
G1T1
NA
12
28
Enhanced Local Bus Controller
G1T3
UTA
13
29
TODT LAST
G2T1
14
30
G2T3
13-81
15
31