MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 876

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Three-Speed Ethernet Controllers
Table 14-119
14.5.3.11.6 Timer Status Register (TMR_STAT)
This register requires the eTSEC filer to be enabled (via RCTRL[FILREN]). When eTSEC generates an
interrupt based on the timestamp event for a received packet, the queue ID which the incoming packet will
be sent to is captured in this register. This register update is synchronized with the RXF interrupt of the
corresponding received packet. Writing 1 to any bit of this register clears it.
definition for the TMR_STAT register.
Table 14-121
14.5.3.11.7 Timer Counter Register (TMR_CNT_H/L)
The timer register (TMR_CNT_H/L) represents accurate time in terms clock ticks or in nano-seconds.
Writes to these registers will override the previous time. The register in eTSEC1 is shared for all eTSECs.
This is a read/write register. Figure 14-114 describes the definition for the TMR_CNT_H/L register.
14-128
24–30
26–31
0–21
0–25
Bits
Bits
22
23
31
Offset eTSEC1:0x2_4E14
Reset
W
R
STAT_VEC Timer general purpose status vector. It will store the 6-bit queue number generated by the filer. User
TXP2EN
TXP1EN
0
RXPEN
Name
Name
—
describes the fields of the TMR_PEMASK register fields for the timer.
—
—
describes the fields of the TMR_STAT register.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Reserved
to decode this status vector. For example, user can encode received PTP packet message types
(Sync, Delay_req, Follow_up, Delay_resp, Management) in the filer virtual queue field.
Reserved
Transmit PTP packet event 2 enable
Transmit PTP packet event 1 enable
Reserved
Receive PTP packet event enable
Table 14-119. TMR_PEMASK Register Field Descriptions
Table 14-121. TMR_STAT Register Field Descriptions
Table 14-120. TMR_STAT Register Definition
—
All zeros
Description
Description
Figure 14-120
25 26
Freescale Semiconductor
STAT_VEC
Access: Mixed
describes the
31