MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1604

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Debug Features and Watchpoint Facility
must be configured to perform a read before this register contains valid data. This register must be
initialized by software before configuring the TBACR to perform a write command.
Table 25-22
25.3.3
This section describes the context ID registers. The current context ID register (CCIDR) and programmed
context ID registers (PCIDR) are set by software and facilitate debugging complex software.
25.3.3.1
The programmed context ID register (PCIDR), shown in
context ID. This register can be configured to trigger watchpoint events when its value matches the current
context ID register (CCIDR), as controlled by WMCR0[ECEN] and WMCR0[NECEN]. See
Section 25.3.1.1, “Watchpoint Monitor Control Registers 0–1 (WMCR0, WMCR1),”
information.
Table 25-23
25-22
0–31
0–31
Bits
Bits
Offset 0x068
Offset 0x0A0
Reset
Reset
W
W
R
R
Name
Name
TBAD Trace buffer access data. Corresponds to the lower 32 bits of the data read from the trace buffer or to be
PCID
0
0
Context ID Registers
describes the TBADR field.
describes the PCIDR field.
Programmed Context ID Register (PCIDR)
Programmed context ID. Contains the user-programmed context ID. Compared with current context ID for
context-sensitive event triggering
written into the trace buffer, depending on whether software is accessing the array with a read or a write.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Figure 25-16. Trace Buffer Access Data Register (TBADR)
Figure 25-17. Programmed Context ID Register (PCIDR)
Table 25-22. TBADR Field Descriptions
Table 25-23. PCIDR Field Descriptions
All zeros
All zeros
TBAD
PCID
Description
Description
Figure
25-17, contains the user-programmed
Freescale Semiconductor
Access: Read/Write
Access: Read/Write
for more
31
31