MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1369

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

21.3.2.22 Endpoint Control Register n (ENDPTCTRL n )—Non-EHCI
These registers are not defined in the EHCI specification. There is an ENDPTCTRLn register of each
endpoint in a device.
Freescale Semiconductor
31–24
19–18
Offset 0x1C4 (ENDPTCTRL1), 0x1C8 (ENDPTCTRL2), 0x1CA (ENDPTCTRL3),
Reset
15–8
Bits
23
22
21
20
17
16
7
W
R
0x1D0 (ENDPTCTRL4), 0x1D4 (ENDPTCTRL5)
31
Name
TXR
TXD
RXE
TXE
TXT
TXS
TXI
—
—
—
Reserved, should be cleared
TX endpoint enable
0 Disabled
1 Enabled
TX data toggle reset. Whenever a configuration event is received for this endpoint, software must write a one to
this bit in order to synchronize the data PID’s between the Host and device.
TX data toggle inhibit. Used only for test and should always be written as zero. Writing a one to this bit will cause
this endpoint to ignore the data toggle sequence and always transmit DATA0 for a data packet.
0 PID sequencing enabled
1 PID sequencing disabled
Reserved, should be cleared
TX endpoint type
00 Control
01 Isochronous
10 Bulk
11 Interrupt
Note: When only one endpoint (RX or TX, but not both) of an endpoint pair is used, the unused endpoint should
be configured as a bulk type endpoint.
TX endpoint data source. This bit should always be written as 0, which selects the dual port memory/DMA
engine as the source.
TX endpoint stall. This bit will be set automatically upon receipt of a SETUP request if this endpoint is not
configured as a control endpoint. It will be cleared automatically upon receipt of a SETUP request if this endpoint
is configured as a control endpoint.
Software can write a one to this bit to force the endpoint to return a STALL handshake to the host. It will continue
to returning STALL until this bit is either cleared by software or automatically cleared as above.
0 Endpoint OK
1 Endpoint stalled
Reserved, should be cleared
RX endpoint enable
0 Disabled
1 Enabled
—
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
24
TXE TXR TXI — TXT TXD TXS
Table 21-30. ENDPTCTRL x Register Field Descriptions
23
Figure 21-28. Endpoint Control 1 to 5 (ENDPTCTRL n )
22
21
20 19 18
17
All zeros
16
Description
15
—
8
RXE RXR RXI — RXT RXD RXS
7
Universal Serial Bus Interfaces
6
5
Access: Read/Write
4
3
2
1
21-35
0