MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 234

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

L2 Look-Aside Cache/SRAM
Table 6-5
6.3.1.2.2
The L2 cache external write address registers extended address (L2CEWAREAn), shown in
contain the upper 4 bits of the 28-bit L2 cache external write base address.
Table 6-6
6.3.1.2.3
The L2CEWARn/L2CEWAREAn address registers work with the L2 cache external write control
registers 0–3 (L2CEWCRn), shown in
6-14
Offset 0x2_0014
Reset
Offset 0x2_0018
Reset
24–31
28–31
0–23
0–27
Bits
Bits
W
W
R
R
0x2_0024
0x2_0034
0x2_0044
0x2_0028
0x2_0038
0x2_0048
E LOCK
0
0
Figure 6-9. Cache External Write Address Registers Extended Address (L2CEWAREA n )
describes L2CEWARn fields.
describes the fields of L2CEWAREAn.
ADDR
ADDR
Name
Name
1
Figure 6-10. Cache External Write Control Registers (L2CEWCR0–L2CEWCR3)
—
—
L2 Cache External Write Address Registers Extended Address 0–3
(L2CEWAREA n )
L2 Cache External Write Control Registers 0–3 (L2CEWCR n )
2
—
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
3
bits of the base address are in L2CEWAREA n [ADDR].
Reserved
Reserved
address is in L2CEWAR n [ADDR].
Contains the lower 24 bits of the 28-bit L2 cache external write base address. Note that the upper 4
Contains the upper 4 bits of the L2 cache external write base address. Note that the rest of the base
4
Table 6-6. L2CEWAREA n Field Descriptions
Table 6-5. L2CEWAR n Field Descriptions
Figure
6-10, to control cache external write functionality.
—
All zeros
All zeros
Description
Description
SIZMASK
Freescale Semiconductor
Access: Read/Write
Access: Read/Write
27 28
Figure
ADDR
6-9,
31
31