MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1232

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SATA Controller
Figure 19-1
There are four layers in the SATA architecture: application, transport, link, and PHY. The application layer
is responsible for overall ATA command execution, including controlling command block register
accesses. The transport layer is responsible for placing control information and data to be transferred
between the host and device in a packet/frame, known as a frame information structure (FIS). The link
layer is responsible for taking data from the constructed frames, inserting control characters and moving
data to the PHY layer. The PHY layer is responsible for 8B/10B encoding/decoding, then transmitting and
receiving the encoded information as a serial data stream on the wire.
19.2
The SATA controller maintains a queue consisting of up to 16 commands. These commands can be
distributed to a single attached device or, if the system contains a port multiplier, over each of the attached
devices. It is possible to queue queued commands and non-queued commands into the SATA controller,
provided the host software does not break protocol to any particular device (it is illegal to issue a
non-queued command to a device that still has a queued command active as per ATAPI/ATA protocol).
19.2.1
When the host software is preparing to issue a command, it first builds a command descriptor as shown in
Figure
Figure
This list should be defined to exactly match the transfer length as programmed into the command FIS. If
the 16 entries are not sufficient, then an extended entry (ext) can be used to refer to an alternate table. When
19-2
19-28. The format of the command FIS is defined in the Serial ATA 2.5 standard shown in
19-29. The software is also responsible for the creation of a scatter/gather list for data movement.
Command Operation
Command Issue
shows a block diagram of SATA.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
DMA Controller
System Bus
Figure 19-1. SATA Block Diagram
PHY Control Layer
Command Issue
CCSR Registers
Transport Layer
Management
Link Layer
Context
PHY
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