MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1378

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Universal Serial Bus Interfaces
The asynchronous list is a simple circular list of queue heads. The ASYNCLISTADDR register is simply
a pointer to the next queue head. This implements a pure round-robin service for all queue heads linked
into the asynchronous list.
21.5.3
Figure 21-37
high-speed isochronous endpoints. All other transfer types should use queue structures. Isochronous TDs
must be aligned on a 32-byte boundary.
21.5.3.1
The first DWord of an iTD is a pointer to the next schedule data structure.
21-44
1
2
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Host controller read/write; all others read-only.
These fields may be modified by the host controller if the I/O field indicates an OUT.
Status
Status
Status
Status
Status
Status
Status
Status
1
1
1
1
1
1
1
1
Isochronous (High-Speed) Transfer Descriptor (iTD)
Next Link Pointer
illustrates the format of an isochronous transfer descriptor. This structure is used only for
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Transaction 0 Length
Transaction 1 Length
Transaction 2 Length
Transaction 3 Length
Transaction 4 Length
Transaction 5 Length
Transaction 6 Length
Transaction 7 Length
Buffer Pointer (Page 0)
Buffer Pointer (Page 1)
Buffer Pointer (Page 2)
Buffer Pointer (Page 3)
Buffer Pointer (Page 4)
Buffer Pointer (Page 5)
Buffer Pointer (Page 6)
Figure 21-37. Isochronous Transaction Descriptor (iTD)
Next Link Pointer
1
1
1
1
1
1
1
1
ioc
ioc
ioc
ioc
ioc
ioc
ioc
ioc
15
14 13 12
PG
PG
PG
PG
PG
PG
PG
PG
2
2
2
2
2
2
2
2
I/O
11
EndPt
10
9
Transaction 0 Offset
Transaction 1 Offset
Transaction 2 Offset
Transaction 3 Offset
Transaction 4 Offset
Transaction 5 Offset
Transaction 6 Offset
Transaction 7 Offset
8
Maximum Packet Size
Reserved
R
7
Reserved
Reserved
Reserved
Reserved
6
Device Address
5
Freescale Semiconductor
4
00
3
2
2
2
2
2
2
2
2
2
Typ
1
Mult
T 0x00
0
0x0C
0x1C
0x2C
0x3C
0x04
0x08
0x10
0x14
0x18
0x20
0x24
0x28
0x30
0x34
0x38
Offset