MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 692

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Local Bus Controller
Table 13-32
varied.
13-50
TRLX
Option Register Attributes
0
0
0
0
0
0
0
0
0
0
0
0
1
1
lists the signal timing parameters for a GPCM read access as the option register attributes are
LBCTL
LCLK
LCS n
LALE
LOE
LAD
EHTR
TA
A
0
0
0
0
0
0
1
1
1
1
1
1
0
0
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Notes:
t
t
t
RC
ARCS
AOE
XACS
= Read cycle time.
Address
= Address valid to output enable time.
0
0
0
1
1
1
0
0
0
1
1
1
0
0
= Address valid to read chip-select time.
Figure 13-36. GPCM General Read Timing Parameters
Table 13-32. GPCM Read Control Signal Timing
ACS
0X
0X
0X
0X
0X
10
11
10
11
10
11
10
11
10
t
ARCS
t
ARCS
t
1¼
AOE
¼
½
¼
½
0
0
1
2
0
0
1
2
0
Latched Address
1¾+2×SCY
2+2×SCY
1¾+SCY
1½+SCY
1¾+SCY
1½+SCY
Signal Timing (LCLK clock cycles)
2+SCY
2+SCY
1+SCY
1+SCY
2+SCY
2+SCY
1+SCY
1+SCY
t
t
CSRP
CSRP
Read Data
t
RC
t
t
CSRP
OEN
= Output enable negated time.
= Read chip-select assertion period.
t
AOE
1
1
1
1
1
2
1
1
1
1
1
2
1
2
t
OEN
t
OEN
0
0
0
0
0
0
1
1
1
1
1
1
4
4
Freescale Semiconductor
6+2×SCY
7+2×SCY
2+SCY
2+SCY
2+SCY
2+SCY
2+SCY
3+SCY
3+SCY
3+SCY
3+SCY
3+SCY
3+SCY
4+SCY
t
RC