MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1469

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The transaction error bit set in the status field indicates a fulfillment error condition. When a fulfillment
error occurs, the frame after the transfer failed to complete wholly, the device controller will force retire
the ISO-dTD and move to the next ISO-dTD.
It is important to note that fulfillment errors are only caused due to partially completed packets. If no
activity occurs to a primed ISO-dTD, the transaction will stay primed indefinitely. This means it is up to
software discard transmit ISO-dTDs that pile up from a failure of the host to move the data.
Finally, the last difference with ISO packets is in the data level error handling. When a CRC error occurs
on a received packet, the packet is not retried similar to bulk and control endpoints. Instead, the CRC is
noted by setting the Transaction Error bit and the data is stored as usual for the application software to sort
out.
21.8.3.6.1
When it is necessary to synchronize an isochronous data pipe to the host, the (micro)frame number
(FRINDEX register) can be used as a marker. To cause a packet transfer to occur at a specific (micro)frame
number [N], the DCD should interrupt on SOF during frame N-1. When the FRINDEX=N-1, the DCD
must write the prime bit. The USB controller will prime the isochronous endpoint in (micro)frame N-1 so
that the device controller will execute delivery during (micro)frame N.
Freescale Semiconductor
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TX Packet Retired
— MULT counter reaches zero.
— Fulfillment Error [Transaction Error bit is set]
— #Packets Occurred > 0 AND # Packets Occurred < MULT
RX Packet Retired:
— MULT counter reaches zero.
— Non-MDATA Data PID is received
— Overflow Error:
— Packet received is > maximum packet length. [Buffer Error bit is set]
— Packet received exceeds total bytes allocated in dTD. [Buffer Error bit is set]
— Fulfillment Error [Transaction Error bit is set]
— # Packets Occurred > 0 AND # Packets Occurred < MULT
— CRC Error [Transaction Error bit is set]
For TX-ISO, MULT Counter can be loaded with a lesser value in the dTD
Multiplier Override field. If the Multiplier Override is zero, the MULT
Counter is initialized to the Multiplier in the QH.
For ISO, when a dTD is retired, the next dTD is primed for the next frame.
For continuous (micro)frame to (micro)frame operation the DCD should
ensure that the dTD linked-list is out ahead of the device controller by at
least two (micro)frames.
Isochronous Pipe Synchronization
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
NOTE
NOTE
Universal Serial Bus Interfaces
21-135