MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 672

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Local Bus Controller
13.3.1.12 Transfer Error Attributes Register (LTEATR)
The transfer error attributes register (LTEATR) captures source attributes of an error/event.
shows the LTEATR. After LTEATR[V] has been set, software must clear this bit to allow LTESR,
LTEATR, and LTEAR to update following any subsequent events/errors.
13-30
Offset 0x0_50BC
Reset
10–11
13–29
Bits
3–4
6–7
12
30
31
2
5
8
9
W
R
0
WARA Write after read atomic (WARA) error interrupt enable.
RAWA Read after write atomic (RAWA) error interrupt enable.
Name
UCCI
PARI
—
WPI
CSI
CCI
—
—
—
—
2
RWB
Parity and ECC error interrupt enable. Note that uncorrectable read errors may cause the assertion of
core_fault_in, which causes the core to generate a machine check interrupt, unless it is disabled (by clearing
HID1[RFXE]). If RFXE is zero and this error occurs, LTEDR[PARD] must be cleared and PARI must be set to
ensure that an interrupt is generated.
0 Parity and ECC error reporting is disabled.
1 Parity and ECC error reporting is enabled.
Reserved
Write protect error interrupt enable.
0 Write protect error reporting is disabled.
1 Write protect error reporting is enabled.
Reserved
0 WARA error reporting is disabled.
1 WARA error reporting is enabled.
0 RAWA error reporting is disabled.
1 RAWA error reporting is enabled.
Reserved
Chip select error interrupt enable.
0 Chip select error reporting is disabled.
1 Chip select error reporting is enabled.
Reserved
UPM Run pattern command completion Event interrupt enable.
0 UPM Run pattern command completion reporting is disabled.
1 UPM Run pattern command completion reporting is enabled.
FCM command completion Event interrupt enable.
0 Command completion reporting is disabled.
1 Command completion reporting is enabled.
3
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
4
Figure 13-16. Transfer Error Attributes Register (LTEATR
Table 13-18. LTEIR Field Descriptions (continued)
—
10 11
SRCID
All zeros
15 16
Description
PB
19 20
BNK
Freescale Semiconductor
Access: Read/Write
27 28
Figure 13-16
—
30 31
V