MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1253

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 19-20
19.3.4.5
LinkCfg2, shown in
Table 19-21
19.3.4.6
LinkStatus, shown in
Freescale Semiconductor
Offset 0x1_8154
Reset
Offset 0x1_8150
Reset
W
W
R
R
31
31
31–7
5–0
31–0
Bit
Bit
6
describes the LinkCfg1 fields.
describes the LinkCfg2 fields.
Link Layer Configuration Register2 (LinkCfg2)
Link Layer Status Register (LinkStatus)
PRIM_OVR_S
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Name
TATE
Figure
Name
CD
PRIM
—
Figure
Figure 19-21. Link Layer Configuration Register1 (LinkCfg1)
Figure 19-22. Link Layer Status Register (LinkStatus)
19-21, controls the configuration of the link layer.
19-22, indicates the status of the link layer.
Reserved
This bit specifies whether the data used during the primitive override should be a
data character or a primitive. For example, if CD = 1,
PRIM_OVR_STATE = L_SendEOF and PRIM = WTRM, then a WTRM primitive
will be inserted into the datastream instead of an EOF (whenever a rising edge is
seen on PRIM_OVR_EN). If CD = 0, then a normal data character (as specified by
PRIM) is inserted into the datastream instead of the EOF.
Prim override state. These 6 bits are used in the primitive override debug
functionality. When the link layer detects a positive edge on PRIM_OVR_EN, it
overrides the next primitive that would be inserted during the PRIM_OVR_STATE,
with the data specified by the PRIM and CD configuration bits.
Table 19-20. LinkCfg1 Field Descriptions
Table 19-21. LinkCfg2 Field Descriptions
This 32-bit bus specifies the data to be used in the overriding primitive debug
logic, described in the definition of LinkCfg1 register.
—
All zeros
All zeros
PRIM
Description
Description
6
Access: Read/Write
5
Access: Read only
LINK_STATE
SATA Controller
19-23
0
0