MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 830

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Three-Speed Ethernet Controllers
14.5.3.5.8
The MIIMADD register is written by the user.
Table 14-50
14.5.3.5.9
MIIMCON, shown in
14-82
19–23
24–26
27–31 Register Address This field represents the 5-bit register address field of Mgmt cycles. Up to 32 registers can be
0–18
Bits
Bits
30
31
Offset eTSEC1:0x2_4528
Reset
Offset eTSEC1:0x2_452C
Reset
W
W
R
R
Scan Cycle Scan cycle. This bit is cleared by default.
Read Cycle Read cycle. This bit is cleared by default but is not self-clearing once set.
PHY Address
0
0
Name
Name
describes the fields of the MIIMADD register.
—
—
MII Management Address Register (MIIMADD)
MII Management Control Register (MIIMCON)
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
0 Normal operation.
1 The MII management continuously performs read cycles. This is useful for monitoring link fail, for
0 Normal operation.
1 The MII management performs a single read cycle upon the transition of this bit from 0 to 1 using the
example.
PHY address (at MIIMADD[PHY Address]) and the register address (at MIIMADD[Register
Address]). The 0-to-1 transition of this bit also causes the MIIMIND[Busy] bit to be set. The read is
complete when the MIIMIND[Busy] bit clears. Data is returned in register MIIMSTAT[PHY Status].
Figure
Reserved
This field represents the 5-bit PHY address field of Mgmt cycles. Up to 31 PHYs can be addressed
(0 is reserved). Its default value is 0x00.
Reserved
accessed. Its default value is 0x00.
Figure 14-47. MII Mgmt Control Register Definition
Table 14-49. MIIMCOM Descriptions (continued)
14-47, is written by the user.
Figure 14-46. MIIMADD Register Definition
—
Table 14-50. MIIMADD Field Descriptions
—
Figure 14-46
All zeros
All zeros
15 16
Description
Description
shows the MIIMADD register.
18 19
PHY Address
PHY Control
23 24
Freescale Semiconductor
—
26 27
Access: Read/Write
Register
Address
Access: WO
31
31