MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 318

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DDR Memory Controller
Table 8-28
8.4.1.23
The DDR Register Control Word 1 register should be programmed with the intended values of the register
control words if DDR_SDRAM_CFG[RCW_EN] is set. Each 4-bit field represents the value that is placed
on MA[3], MA[4], MBA[0], and MBA[1] during register control word writes.
8-44
Offset 0x180
Reset
t
12–15
16–31
0–11
Bits
W
R
0
RCW0
describes the DDR_SR_CNTR fields.
SR_IT
Name
DDR SDRAM Register Control Word 1 (DDR_SDRAM_RCW_1)
—
—
3
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
4
Figure 8-24. DDR Register Control Word 1 (DDR_SDRAM_RCW_1)
RCW1
Reserved, should be cleared.
Self Refresh Idle Threshold. Defines the number of DRAM cycles that must pass while the DDR
controller is idle before it will enter self refresh. Anytime a transaction is issued to the DDR
controller, it will reset its internal counter. When a new transaction is received by the DDR
controller, it will exit self refresh and reset its internal counter. If this field is zero, then the
described power savings feature is disabled. In addition, if a non-zero value is programmed into
this field, then the DDR controller will exit self refresh anytime a transaction is issued to the DDR
controller, regardless of the reason self refresh was initially entered.
If this field is set to a non-zero value, then DDR_SDRAM_CFG[SREN] must also be set.
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100-1111
Reserved, should be cleared.
7
Table 8-28. DDR_SR_CNTR Field Descriptions
8
RCW2
Automatic self refresh entry disabled
2^10 DRAM clocks
2^12 DRAM clocks
2^14 DRAM clocks
2^16 DRAM clocks
2^18 DRAM clocks
2^20 DRAM clocks
2^22 DRAM clocks
2^24 DRAM clocks
2^26 DRAM clocks
2^28 DRAM clocks
2^30 DRAM clocks
Reserved
11 12
RCW3
All zeros
15 16
Description
RCW4
19 20
RCW5
23 24
RCW6
Freescale Semiconductor
Access: Read/Write
27 28
RCW7
31