MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 614

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

I
The scenario above assumes that the I
an I
I
one interrupt, which is sourced by the dual I
11.5.3
Transmission or reception of a byte automatically sets the data transferring bit (I2CSR[MCF]), which
indicates that one byte has been transferred. The I
is generated to the processor if the interrupt function is enabled during the initialization sequence
(I2CCR[MIEN] is set). In the interrupt handler, software must take the following steps:
When an interrupt occurs at the end of the address cycle, the master remains in transmit mode. If master
receive mode is required, I2CCR[MTX] must be toggled at this stage. See
Service Routine Flowchart.”
If the interrupt function is disabled, software can service the I2CDR in the main program by monitoring
I2CSR[MIF]. In this case, I2CSR[MIF] must be polled rather than I2CSR[MCF] because MCF behaves
differently when arbitration is lost. Note that interrupt or other bus conditions may be detected before the
I
may be needed in order to give the I
During slave-mode address cycles (I2CSR[MAAS] is set), I2CSR[SRW] should be read to determine the
direction of the subsequent transfer and I2CCR[MTX] should be programmed accordingly. For
slave-mode data cycles (MAAS is cleared), I2CSR[SRW] is not valid and I2CCR[MTX] must be read to
determine the direction of the current transfer. See
for more details.
11.5.4
A data transfer ends with a STOP condition generated by the master device. A master transmitter can
generate a STOP condition after all the data has been transmitted.
If a master receiver wants to terminate a data transfer, it must inform the slave transmitter by not
acknowledging the last byte of data (by setting the transmit acknowledge bit (I2CCR[TXAK])) before
reading the next-to-last byte of data. At this time, the next-to-last byte of data has already been transferred
on the I
set). Before the interrupt service routine reads the last byte of data, a STOP condition must first be
generated.
11-22
2
2
2
C Interfaces
C interrupt handler can handle the interrupt. Note that the interrupts for I
C signals have time to settle. Thus, when polling I2CSR[MIF] (or any other I2CSR bits), software delays
3. Write the slave address being called into I2CDR. The data written to I2CDR[0–6] comprises the
2
1. Clear I2CSR[MIF]
2. Read the contents of the I
C interrupt is generated (provided interrupt reporting is enabled with I2CCR[MIEN] =1) so that the
slave calling address. I2CCR[MTX] indicates the direction of transfer (transmit/receive) required
from the slave.
mode. Note that this causes I2CSR[MCF] to be cleared. See
Routine Flowchart.”
2
C interface, so the last byte does not receive the data acknowledge (because I2CCR[TXAK] is
Post-Transfer Software Response
Generation of STOP
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
2
C data register (I2CDR) in receive mode or write to I2CDR in transmit
2
C signals sufficient time to settle.
2
C interrupt bit (I2CSR[MIF]) is cleared. If MIF is set at any time,
2
C controller.
2
C interrupt bit (I2CSR[MIF]) is also set and an interrupt
Section 11.5.8, “Interrupt Service Routine Flowchart,”
Section 11.5.8, “Interrupt Service
2
C1 and I
Section 11.5.8, “Interrupt
2
C2 are combined into
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