MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 682

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Local Bus Controller
Table 13-28
Table 13-29
13-40
17–21
23–31
14–19
21–31
0–16
0–13
Bits
Bits
22
20
Name
Name
MS
MS
describes FPAR fields for small page devices.
—
CI
describes FPAR fields for large page devices.
—
CI
PI
PI
Table 13-29. FPAR Field Descriptions, Large Page Device (ORx[PGS] = 1)
Table 13-28. FPAR Field Descriptions, Small Page Device (ORx[PGS] = 0)
Reserved
Page index. PI indexes the page in NAND Flash EEPROM at the current block defined by FBAR, and
locates the corresponding transfer buffer in the FCM buffer RAM.
The 3 LSBs of PI index one of the eight 1 Kbyte buffers in the FCM buffer RAM as follows:
000 The page is transferred to/from FCM buffer 0, address offsets 0x0000–0x03FF
001 The page is transferred to/from FCM buffer 1, address offsets 0x0400–0x07FF
010 The page is transferred to/from FCM buffer 2, address offsets 0x0800–0x0BFF
011 The page is transferred to/from FCM buffer 3, address offsets 0x0C00–0x0FFF
100 The page is transferred to/from FCM buffer 4, address offsets 0x1000–0x13FF
101 The page is transferred to/from FCM buffer 5, address offsets 0x1400–0x17FF
110 The page is transferred to/from FCM buffer 6, address offsets 0x1800–0x1BFF
111 The page is transferred to/from FCM buffer 7, address offsets 0x1C00–0x1FFF
Main/spare region locator. In the case that FBCR[BC] = 0, MS is treated as 0.
0 Data is transferred to/from the main region of the FCM buffer; that is, the first 512 bytes of the buffer
1 Data is transferred to/from the spare region of the FCM buffer; that is, the second 512 bytes of the
Column index. CI indexes the first byte to transfer to/from the main or spare region of the NAND Flash
EEPROM and corresponding transfer buffer. In the case that FBCR[BC] = 0, CI is treated as 0. For MS
= 0, CI can range 0x000–0x1FF; for MS = 1, CI can range 0x000–0x00F.
Reserved
Page index. PA indexes the page in NAND Flash EEPROM at the current block defined by FBAR, and
locates the corresponding transfer buffer in the FCM buffer RAM.
The LSB of PI indexes one of the two 4 Kbyte buffers in the FCM buffer RAM as follows:
0 The page is transferred to/from FCM buffer 0, address offsets 0x0000–0x0FFF
1 The page is transferred to/from FCM buffer 1, address offsets 0x1000–0x1FFF
Main/spare region locator. In the case that FBCR[BC] = 0, MS is treated as 0.
0 Data is transferred to/from the main region of the FCM buffer; that is, the first 2048 bytes of the buffer
1 Data is transferred to/from the spare region of the FCM buffer; that is, the second 2048 bytes of the
Column index. CI indexes the first byte to transfer to/from the main or spare region of the NAND Flash
EEPROM and corresponding transfer buffer. In the case that FBCR[BC] = 0, CI is treated as 0. For
MS = 0, CI can range 0x000–0x7FF; for MS = 1, CI can range 0x000–0x03F.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
are used as the starting address.
buffer are used as the starting address, but only an initial 16 bytes of spare region are defined.
are used as the starting address.
buffer are used as the starting address, but only an initial 64 bytes of spare region are defined.
Description
Description
Freescale Semiconductor