MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 907

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The encoding of the eTSEC GMII signals in this FIFO mode is shown in
In this mode flow control can control only the decision to continue transmitting packets, as packet transfers
cannot be suspended once started.
14.6.2.4
The encoded packet 8-bit FIFO mode uses the signals shown in
four states that can be associated with each beat of data. This mode should be used where invalid bytes can
appear between the start and end of packet. Illustrative timing of the encoded packet FIFO mode is shown
in
The encoding of the eTSEC GMII signals in this FIFO mode is shown in
In this mode flow control can cause an indefinite number of invalid data bytes to be transferred. This is the
only mode in which an empty eTSEC Tx FIFO also causes a string of invalid data bytes to be transmitted
rather than causing an underrun error.
14.6.2.5
Refer to
Freescale Semiconductor
Figure
Section 14.7.1.7, “8-Bit FIFO Mode”
14-140.
Valid data, start of packet
Valid data
Valid data, end of packet
Error
8-Bit Encoded Packet FIFO Mode
FIFO Interface Signal Summary
TX_ER/RX_ER
TX_EN/RX_DV
Valid data, start of packet
Valid data
Valid data, end of packet
Data not valid
TXD/RXD[7:0]
TX/RX_CLK n
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Condition
Table 14-147. Signal Encoding for GMII-Style 8-Bit FIFO
Condition
Table 14-148. Signal Encoding for Encoded 8-Bit FIFO
Figure 14-140. 8-Bit Encoded Packet FIFO Timing
SOP
0 to 1 transition at start of cycle
1 to 0 transition at end of cycle
for interface signal details.
TX_EN/RX_DV
TX_EN/RX_DV
1
1
0
0
1
1
Figure
Enhanced Three-Speed Ethernet Controllers
TX_ER/RX_ER
14-140. The control lines encode
1 until TX_EN/RX_DV falls
EOP
Table
Table
0
1
1
0
TX_ER/RX_ER
14-147.
14-148.
0
0
0
14-159