MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 236

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

L2 Look-Aside Cache/SRAM
6.3.1.3.1
The L2 memory-mapped SRAM base address registers (L2SRBARn), shown in
lower 18 bits of the 22-bit SRAM base address.
L2SRBAR bits are described in
When enabled, the windows defined in L2SRBARn and L2SRBAREAn supersede all other mappings of
these addresses for processor and global (snoopable) I/O transactions. Therefore, SRAM windows must
never overlap configuration space as defined by CCSRBAR (see
Control, and Status Registers Base Address Register
windows is discouraged because processor and snoopable I/O transactions would map to the SRAM while
non-snooped I/O transactions would be mapped by the local access windows. Only if all accesses to the
SRAM address range are snoopable can results be consistent if SRAM and local access windows overlap.
6-16
18–31
Offset 0x2_0100
0–17
Reset
Bits
W
R
0x2_0108
0
ADDR Contains the lower 18 bits of the 22-bit L2 memory-mapped SRAM base address; the upper 4 bits are
Name
—
Figure 6-11. L2 Memory-Mapped SRAM Base Address Registers (L2SRBAR n )
contained in L2SRBAREA n [ADDR]. (Note that some of these bits may not be needed, depending on how the
L2 cache is partitioned.) The combined base address from L2SRBAREA n [ADDR] || L2SRBAR n [ADDR] is
used as follows:
SRAM Partition
64 Kbytes
128 Kbytes
256 Kbytes
512 Kbytes
Unused bits of the base address are masked off by the hardware.
Reserved
L2 Memory-Mapped SRAM Base Address Registers 0–1 (L2SRBAR n )
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Bits Required for SRAM Offset
ADDR
Table
Table 6-8. L2SRBAR n Field Descriptions
16
17
18
19
6-8.
(CCSRBAR).”) Overlapping SRAM and local access
All zeros
Description
17 18
Bits Used for Actual Base Address
20 (0–19)
19 (0–18)
18 (0–17)
17 (0–16)
Section 4.3.1.1.2, “Configuration,
Figure
—
Freescale Semiconductor
Access: Read/Write
6-11, contain the
31