MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 431

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 10
Security Engine (SEC) 3.0
This chapter describes the functionality of Freescale’s integrated security engine (SEC 3.0). It addresses
the following topics:
The SEC 3.0 is designed to off-load computationally intensive security functions, such as key generation
and exchange, authentication, and bulk encryption from the processor core of the SoC. It is optimized to
process all cryptographic algorithms associated with IPsec, IKE, SSL/TLS, iSCSI, SRTP, 802.11i,
WiMAX, 3G, A5/3 for GSM and EDGE, and GEA3 for GPRS. The SEC 3.0 is derived from integrated
security cores found in other members of the PowerQUICC II and PowerQUICC III families.
The security engine includes eight different execution units (EUs). Where data flows in and out of an EU,
each has buffer FIFOs of at least 256 bytes. EU types and features include the following:
Freescale Semiconductor
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Section 10.1, “SEC Architecture Overview
Section 10.2, “Configuration of Internal Memory Space
Section 10.3, “Descriptors
Section 10.4, “Polychannel”
Section 10.5, “Controller”
Section 10.5.1, “Bus Transfers”
Section 10.6, “Power Saving Mode
Section 10.7, “Execution Units”
AESU—Advanced Encryption Standard unit
— Implements the Rijndael symmetric key cipher per U.S. National Institute of Standards and
— Modes providing data confidentiality: ECB, CBC, CCM, Counter, GCM, XTS, CBC-RBP,
— Modes providing data authentication: CCM, GCM, CMAC (OMAC1), and XCBC-MAC.
— 128-, 192-, or 256-bit key lengths (only 128-bit keys in XCBC-MAC)
— ICV (integrity check vector) checking in CCM, GCM, CMAC (OMAC1), and XCBC-MAC
— XOR operations on 2–6 sources for RAID
AFEU—ARC4 execution unit
— Implements a stream cipher compatible with the RC4 algorithm
— 8- to 128-bit programmable key
CRCU—Cyclical redundancy check unit
Technology (NIST) Federal Information Processing Standard (FIPS) 197.
OFB-128, and CFB-128.
mode
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
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