MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 808

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Three-Speed Ethernet Controllers
14.5.3.3.4
The RQUEUE register enables each of the RxBD rings 0–7. By default, RxBD ring 0 is enabled.
Figure 14-27
Table 14-32
14-60
Offset eTSEC1:0x2_4314;
16–23
Reset
\
Bits
0–7
10
11
12
13
14
15
24
8
9
W
R
eTSEC3:0x2_6314
0
0 0 0 0 0 0 0 0
Name
EN0
EX0
EX1
EX2
EX3
EX4
EX5
EX6
EX7
—
—
describes the RQUEUE register.
—
describes the definition for the RQUEUE register.
Receive Queue Control Register (RQUEUE)
Reserved
Receive queue 0 extract enable.
0 Data transferred by DMA to this RxBD ring is not extracted to cache.
1 Data transferred by DMA to this RxBD ring undergoes extraction according to ATTR register.
Receive queue 1 extract enable.
0 Data transferred by DMA to this RxBD ring is not extracted to cache.
1 Data transferred by DMA to this RxBD ring undergoes extraction according to ATTR register.
Receive queue 2 extract enable.
0 Data transferred by DMA to this RxBD ring is not extracted to cache.
1 Data transferred by DMA to this RxBD ring undergoes extraction according to ATTR register.
Receive queue 3 extract enable.
0 Data transferred by DMA to this RxBD ring is not extracted to cache.
1 Data transferred by DMA to this RxBD ring undergoes extraction according to ATTR register.
Receive queue 4 extract enable.
0 Data transferred by DMA to this RxBD ring is not extracted to cache.
1 Data transferred by DMA to this RxBD ring undergoes extraction according to ATTR register.
Receive queue 5 extract enable.
0 Data transferred by DMA to this RxBD ring is not extracted to cache.
1 Data transferred by DMA to this RxBD ring undergoes extraction according to ATTR register.
Receive queue 6 extract enable.
0 Data transferred by DMA to this RxBD ring is not extracted to cache.
1 Data transferred by DMA to this RxBD ring undergoes extraction according to ATTR register.
Receive queue 7 extract enable.
0 Data transferred by DMA to this RxBD ring is not extracted to cache.
1 Data transferred by DMA to this RxBD ring undergoes extraction according to ATTR register.
Reserved
Receive queue 0 enable.
0 RxBD ring is not queried for reception. In effect the receive queue is disabled.
1 RxBD ring is queried for reception.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
7
EX0 EX1 EX2 EX3 EX4 EX5 EX6 EX7
8
1
0
9
10
0
Figure 14-27. RQUEUE Register Definition
Table 14-32. RQUEUE Field Descriptions
11
0
12
0
13
0
14
0
15
0
Description
16
0 0 0 0 0 0 0 0
—
23
EN0 EN1 EN2 EN3 EN4 EN5 EN6 EN7
24
1
25
0
26
0
Freescale Semiconductor
27
0
Access: Read/Write
28
0
29
0
30
0
31
0