MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1343

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 21-6
21.3.1.5
This register is not defined in the EHCI specification. DCIVERSION is a two-byte register containing a
BCD encoding of the device controller interface. The most-significant byte of the register represents a
major revision and the least-significant byte is the minor revision.
register.
Freescale Semiconductor
31–16
Offset 0x120
Reset
15–8
Bits
7–4
3
2
1
0
W
R
15
0
Name
EECP
ASP
ADC
PFL
IST
—
—
provides bit descriptions for the HCCPARAMS register.
Device Controller Interface Version (DCIVERSION)—Non-EHCI
0
Reserved, should be cleared.
EHCI extended capabilities pointer. Indicates the existence of a capabilities list. A value of 0x00 indicates
no extended capabilities are implemented. A non-zero value in this register indicates the offset in PCI
configuration space of the first EHCI extended capability. The pointer value must be 0x40 or greater if
implemented to maintain the consistency of the PCI header defined for this class of device.
This field is always 0.
Isochronous scheduling threshold. Indicates, relative to the current position of the executing host controller,
where software can reliably update the isochronous schedule. When bit 7 is zero, the value of the least
significant 3 bits indicates the number of microframes a host controller can hold a set of isochronous data
structures (one or more) before flushing the state. When bit 7 is a one, then host software assumes the host
controller may cache an isochronous data structure for an entire frame.
This field is always 0.
Reserved, should be cleared.
Asynchronous schedule park capability. Indicates whether the USB module supports the park feature for
high-speed queue heads in the asynchronous schedule. The feature can be disabled or enabled and set to
a specific level by using the asynchronous schedule park mode enable and asynchronous schedule park
mode count fields in the USBCMD register.
This field is always 1 (park feature supported).
Programmable frame list flag. Indicates whether system software can specify and use a frame list length
less that 1024 elements. Frame list size is configured via the USBCMD register frame list size field. The
frame list must always be aligned on a 4K page boundary. This requirement ensures that the frame list is
always physically contiguous.
This field is always 1.
64-bit addressing capability. Always 0; 64-bit addressing is not supported.
0 Data structures use 32-bit address memory pointers
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
0
Table 21-6. HCCPARAMS Register Field Descriptions
Figure 21-6. Device Interface Version (DCIVERSION)
0
0
0
0
DCIVERSION
0
Description
0
0
Figure 21-6
0
0
shows the DCIVERSION
Universal Serial Bus Interfaces
0
Access: Read-only
0
0
21-9
1
0