MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1025

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

15.5.1
The following is a description of unusual DMA paths including explanations of why some functional
blocks cannot serve as DMA targets. The following topics are addressed:
15.5.1.1
The L1 cache cannot be a direct DMA target because it cannot be directly addressed by software. However,
DMA access into the L1 cache occurs indirectly if a block of memory that is cached in the L1 is specified
as the DMA target. This effect is deterministic if the target memory block was locked into the L1 with
cache locking instructions.
15.5.1.2
Because any internal register can be addressed with the four-channel DMA controller, configuration,
control, and status registers throughout the device are valid DMA targets. However, the primary purpose
of DMA—to reduce processor load by moving large blocks of data— is not served by DMA transfers of
configuration data. For example, while it is possible to DMA into the I
interrupt controller (PIC), doing so is extremely inefficient and is seldom beneficial in normal operation.
The overhead of creating DMA descriptors far exceeds any savings in CPU cycles.
15.5.1.3
The I
“DMA to Configuration, Control, and Status Registers,”
data register (I2CDR).
15.5.1.4
The DUART provides complete and sophisticated DMA support which is described in
“DUART,”
Freescale Semiconductor
•
•
•
•
2
C controller is not transparent to DMA transfers. Observe the caveats listed in
DMA transaction initiators (masters)
DMA targets, that is, data sources or destinations
Transparency of the bus controllers to DMA transactions
What is useful as opposed to what is possible. For example, any register can be addressed through
an internal control bus, which means configuration and control registers can be DMA targets.
specifically,
Unusual DMA Scenarios
DMA to Core
DMA to Configuration, Control, and Status Registers
DMA to I
DMA to DUART
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
2
Section 12.4.5, “FIFO Mode.”
C
when accessing any I
2
C controller or programmable
2
C register, including the
Section 15.5.1.2,
Chapter 12,
DMA Controller
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