MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 932

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Three-Speed Ethernet Controllers
14.6.5.2.1
Unless the filer is disabled, every received frame from the Ethernet MAC or FIFO interface initiates a
search of the receive queue filer table, starting at entry 0. The table search is terminated as soon as an entry
is found whose contents match a property of the frame. Accordingly, software must guarantee that at least
one entry results in a match—even if only to set a default receive queue index.
Since eTSEC searches the table at a rate of two entries every system clock cycle, all 256 entries can be
searched in the time taken to receive a 64-byte Ethernet frame.
Each entry of the receive queue filer table specifies a simple match rule for determining how to process
the received frame. The elements of a filing rule, expressed in the RQCTRL and RQPROP fields, are
summarized as follows:
14-184
•
•
•
•
The PID field in RQCTRL identifies what property is being matched against RQPROP. The eTSEC
supports 16 properties, some of which are different portions of the same header field. Reserved or
unused bits in RQPROP are read as zero. See
Property Register (RQFPR),” on page 14-65
values.
The Q field in RQCTRL identifies which one of 64 virtual receive queues the frame should be filed
to (sent through DMA) in the event of a filing rule match that accepts the frame. The physical
RxBD ring this queue maps to is controlled by the RCTRL[FSQEN] bit. If RCTRL[FSQEN] = 0,
the three least significant bits of the Q field indicate which physical RxBD ring hosts the queue. If
RCTRL[FSQEN] = 1, RxBD ring 0 hosts all receive queues, but the RxFCB[RQ] field allows
software to distinguish queues by ID. In all cases if Q maps to a RxBD ring that is not currently
enabled, the frame is discarded with an IEVENT[FIQ] error.
The REJ field in RQCTRL controls whether the frame is to be rejected (REJ = 1) or filed (REJ =
0) upon a filing rule match. Rejected frames occupy Rx FIFO space, but do not consume memory
bus cycles.
The CMP field in RQCTRL determines how property PID is compared against RQPROP. Equality,
inequality, greater-or-equal, and less-than compares are available.
Filing Rules
Access Index
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
RQFAR
(Access through RQFCR)
Figure 14-148. Structure of the Receive Queue Filer Table
Control/interpretation
entry 255
Entry 0
Entry 1
Entry 2
RQCTRL
RQCTRL
RQCTRL
RQCTRL
32 Bits
for a list of all properties and their associated PID
Section 14.5.3.3.8, “Receive Queue Filer Table
RQPROP
RQPROP
RQPROP
RQPROP
32 Bits
Property Constant
(Access through RQF
Filer
Table
Search
Sequence
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