MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 930

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Three-Speed Ethernet Controllers
For stack L2 (that is, more than one ethertypes) header, the Ethernet parser traverses through the header
until it finds the last valid ethertype or the ethertype is unsupported.
Ethernet header parser recognizes for stack L2 header.
The L3 parser is enabled by RCTRL[PRSDEP] = 10 or 11. It begins when the Ethernet parser ends and a
valid IPv4/v6 ethertype is found. The L4 header is enabled by RCTRL[PRSDEP] = 11. It begins when the
L3 parser ends and a valid TCP/UDP next protocol is found and no fragment frame is found. The primary
functionalities of L3(IPv4/6) and L4(TCP/UDP) parsers are as follows:
14-182
Note: * means that it is the next protocol
Row—Next Supported L2
Column—Current L2
•
•
•
•
JUMBO/SNAP
— JUMBO and SNAP header
— IPV4
— IPV6
— VLAN
— MPLSU/MPLSM
— PPPOES
— ARP
IP recognition (v4/v6, ARP, encapsulated protocol)
IP header checksum verification
IPv4/6 over IPv4/6 (tunneling)—parse headers and find layer 4 protocol
IP layer 4 protocol/next header extraction
LLC/SNAP
Ethertype
Ethertype
MPLSM
MPLSU
PPOES
VLAN
IPV4
IPV6
ARP
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
SNAP
Table 14-160. Supported Stack L2 Ethernet Headers
LLC/
N
N
N
N
Y
N
N
N
N
JUMBO/
SNAP
N
N
N
N
N
N
N
N
Y
IPV4
Y*
Y*
Y
Y
N
N
Y
Y
N
IPV6
Y*
Y*
Y
Y
N
N
Y
Y
N
VLAN
N
N
N
N
N
N
Y
Y
Y
Table 14-160
MPLSU
N
N
N
Y
Y
Y
Y
Y
y
MPLSM
Y
Y
N
N
Y
Y
Y
Y
N
describes what the
Freescale Semiconductor
PPOES
Y
Y
N
N
Y
N
N
N
N
ARP
N
N
N
N
N
N
Y
Y
Y