MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1007

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

15.3.1.11
The next list descriptor address registers, shown in
the next list descriptor in memory. If the contents are transferred to the current list descriptor address
register they become effective for the current transfer in extended chaining mode.
Table 15-17
Figure 15-19
Table 15-19
Freescale Semiconductor
Offset 0x13C
Reset
Offset 0x138
Reset
27–30
W
R
W
0–26
28–31
Bits
R
0–27
Bits
31
0x1BC
0x23C
0x2BC
0
0x1B8
0x238
0x2B8
0
EOLSD End-of-lists descriptor. This bit is ignored in direct mode.
NLSDA Next list descriptor address. Contains the low-order bits of the 36-bit next descriptor address of the
Name
describes the fields of the ENLSDARn.
describes the fields of the NLSDARn.
describes the definition for the NLSDARn registers.
—
Next List Descriptor Address Registers (NLSDAR n and ENLSDAR n )
Figure 15-18. Extended Next List Descriptor Address Registers (ENLSDAR n )
ENLSDA
Name
—
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
buffer descriptor in memory. The descriptor must be aligned on a 32-byte boundary.
Reserved
0 This list descriptor is not the last list descriptor in memory.
1 This list descriptor is the last list descriptor in memory. If this bit is set, then the DMA controller
Figure 15-19. Next List Descriptor Address Registers (NLSDAR n )
halts after the last link descriptor transaction is finished.
Reserved
Next list descriptor extended address bits (upper 4 bits of 36-bit address)
Table 15-18. ENLSDAR n Field Descriptions
Table 15-19. NLSDAR n Field Descriptions
NLSDA
—
Figure 15-18
All zeros
All zeros
Description
Description
and
Figure
15-19, contain the address for
26
27
Access: Read/Write
—
27 28
Access: Mixed
DMA Controller
30
ENLSDA
EOLSD
31
15-21
31