MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 864

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Three-Speed Ethernet Controllers
Table 14-108
14.5.3.7.2
The GADDRn registers are written by the user. Together these registers represent, depending on
RCTRL[GHTX], either the 256 entries of the group address hash table, or the last 256 entries of the
extended group address hash table used in the address recognition process. The user can enable a hash
entry by setting the appropriate bit. A hash table hit occurs if the DA CRC result points to an enabled hash
entry.
Table 14-108
14.5.3.8
This section provides detailed descriptions of the registers used to configure the FIFO interface. All of the
registers are 32 bits wide. The ECNTRL[FIFM] bit is set to indicate that data transfers take place over this
interface. Please refer to
protocols available.
14.5.3.8.1
The FIFO Configuration Register configures and enables the 8-bit FIFO interface.
14-116
0–31 IGADDR n Represents the 32-bit value associated with the corresponding register. When RCTRL[GHTX] = 0,
0–31
Bits
Bits
Offset eTSEC1:0x2_4880+ 4 n ;
Reset
Figure 14-104
W
R
GADDR n Represents the 32-bit value associated with the corresponding register. When RCTRL[GHTX] = 0,
Name
eTSEC3:0x2_6880+ 4 n
Name
0
FIFO Registers
describes the fields of the IGADDRn register.
describes the fields of the GADDRn register.
Group Address Registers 0–7 (GADDR n )
FIFO Configuration Register (FIFOCFG)
IGADDR0 contains entries 0–31 of the 256-entry individual hash table and IGADDR7 represents entries
224–255. When RCTRL[GHTX] = 1, IGADDR0 contains entries 0–31 of the 512-entry extended group hash
table and IGADDR7 represents entries 224–255.
GADDR0 contains entries 0–31 of the 256-entry group hash table and GADDR7 represents entries
224–255. When RCTRL[GHTX] = 1, GADDR0 contains entries 256–287 of the 512-entry extended group
hash table and GADDR7 represents entries 480–511.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
describes the definition for the GADDRn register.
Section 14.6.2, “Connecting to FIFO
Figure 14-104. GADDR n Register Definition
Table 14-107. IGADDR n Field Descriptions
Table 14-108. GADDR n Field Descriptions
GADDR n
All zeros
Description
Description
Interfaces,” for details of the signaling
Freescale Semiconductor
Access: Read/Write
31