MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1687
![BOARD DEV SYSTEM MPC8536E](/photos/29/8/290884/mpc8536eimg_sml.jpg)
MPC8536DS
Manufacturer Part Number
MPC8536DS
Description
BOARD DEV SYSTEM MPC8536E
Manufacturer
Freescale Semiconductor
Series
PowerQUICC III™r
Type
MPUr
Datasheets
1.MPC8536EBVTAVLA.pdf
(127 pages)
2.MPC8536EBVTAVLA.pdf
(1706 pages)
3.MPC8536DS.pdf
(2 pages)
4.MPC8536DS.pdf
(126 pages)
Specifications of MPC8536DS
Contents
Board, Software and Documentation
Processor Series
MPC85xx
Core
e500
Data Bus Width
32 bit
Maximum Clock Frequency
667 MHz
Operating Supply Voltage
- 0.3 V to + 1.21 V
Maximum Operating Temperature
+ 105 C
Data Ram Size
32 KB
Interface Type
SPI, USB
Program Memory Type
DDR2, DDR3, SDRAM
Core Size
32 Bit
Program Memory Size
544KB
Cpu Speed
1.5GHz
Digital Ic Case Style
BGA
No. Of Pins
783
Supply Voltage Range
0.95V To 1.05V
Rohs Compliant
Yes
For Use With/related Products
MPC8536
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- MPC8536EBVTAVLA PDF datasheet
- MPC8536EBVTAVLA PDF datasheet #2
- MPC8536DS PDF datasheet #3
- MPC8536DS PDF datasheet #4
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- Download datasheet (15Mb)
A
Address maps
Address mask (LBC), 13-13
Address translation and mapping units (ATMUs)
Addressing
AFEU
Alignment, byte (PCI/PCI-X), 16-49
Arbitration
ARC Four execution unit (AFEU), 10-88
Architecture
ASLEEP (global utilities asleep) signal, 23-2
ATMUs, see Address translation and mapping units
Freescale Semiconductor
addressing on PCI/PCI-X bus, 16-47
inbound windows, 2-10
local access windows, 2-3–2-10
outbound windows, 2-9
PCI bus addressing, 16-48
context, 10-96
context memory, 10-96, 10-97
data size register, 10-90
FIFOs, 10-97
interrupt control register, 10-94
interrupt status register, 10-92
key registers, 10-97
key size register, 10-89
mode register, 10-89
reset control register, 10-91
status register, 10-62, 10-91, 10-138, 10-157
I
PCI/PCI-X interface, 16-5, 16-42
overview, 1-3
2
C interface
illegal interactions between inbound ATMUs and local
PCI Express, 17-25
PCI/PCI-X—4 windows, 2-10, 16-19
see also Local access windows
PCI Express, 17-20
PCI/PCI-X—4 windows, 16-15
configuration space, 16-48
I/O space, 16-48
memory space, 16-47
arbitration control, 11-15
loss of arbitration—forcing of slave mode, 11-24
procedure for arbitration, 11-15
endpoint (EP) mode, 17-25
root complex (RC) mode, 17-25
access windows, 2-10
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Index
B
Battery backup, self-refresh mode, 8-94
Big-endian, 21-6
Block diagrams
Boot mode
Boot page translation, 4-7
Boot ROM location (POR), 4-14
Boot sequencer
Buffer descriptors, see eTSEC, buffer descriptors
Burst operations (PCI)
Bus operations
Byte alignment (PCI/PCI-X), 16-49
C
Chaining
CKSTP_IN (global utilities checkstop in) signal, 23-2
CKSTP_OUT (global utilities checkstop out) signal, 23-3
CLK_OUT (global utilities clock out) signal, 23-3, 23-33
Clocks
DDR controller, 8-2, 8-60
debug modes, watchpoint monitor, and trace buffer, 25-1
DMA controller, 15-1
DUART, 12-2
e500 coherency module (ECM), 7-1
eTSEC, 14-2
GPIOn module, 22-1
I
interrupt controller (PIC), 9-1
L2 cache/SRAM, 6-1
local bus controller (LBC), 13-1
PCI Express, 17-2
PCI/PCI-X controller, 16-1
performance monitor, 24-2
CPU holdoff (POR), 4-17, 7-4
POR status register (PORBMSR), 23-6
boot holdoff mode (POR), 4-18, 7-4
boot page translation, 4-7
I
overview, 4-8
POR configuration, 4-18
see PCI/PCI-X controller, bus protocol
PCI/PCI-X, see PCI/PCI-X controller, bus protocol
performance monitor events, 24-27
DDR clock distribution, 8-76
DDR controller clock disable, 23-32, 23-33
2
2
C interface, 11-1
C interface, 11-2, 11-17–11-20
Index-1
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