MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1132

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PCI Express Interface Controller
17.3.6.4
The PCI Express error capture status register, shown in
captured when an error occurs. Note that no further error capturing is performed until the ECV bit is
cleared.
Table 17-26
17.3.6.5
Together with the other PCI Express error capture registers, PEX_ERR_CAP_R0 allows vital error
information to be captured when an error occurs. Different error information is reported depending on
whether the error source is from an outbound transaction from an internal source or from an inbound
transaction from an external source; the source of the captured error is reflected in
PEX_ERR_CAP_STAT[GSID]. Note that after the initial error is captured, no further capturing is
performed until the PEX_ERR_CAP_STAT[ECV] bit is clear.
17-36
Offset 0xE20
Reset
26–30 GSID Global source ID. This field indicates the internal platform global source ID that the error transaction
0–24
Bits
25
31
W
R
0
Name
ECV Error capture valid. This bit indicates that the capture registers 0-3 contain valid info. This bit when set
TO
—
describes the fields of the PCI Express error capture status register.
Figure 17-27. PCI Express Error Capture Status Register (PEX_ERR_CAP_STAT)
PCI Express Error Capture Status Register (PEX_ERR_CAP_STAT)
PCI Express Error Capture Register 0 (PEX_ERR_CAP_R0)
Reserved
Transaction originator. This field Indicates whether the originator of the transaction is from
PEX_CONFIG_ADDR/PEX_CONFIG_DATA.
1 Transaction originated from PEX_CONFIG_ADDR/PEX_CONFIG_DATA.
0 Transaction not originated from PEX_CONFIG_ADDR/PEX_CONFIG_DATA.
originates. This field only applies to non PEX_CONFIG_ADDR/PEX_CONFIG_DATA transactions.
00000
00001
00010
00011
00101
01101
01010
All other settings reserved.
indicates that the captured registers contain valid capturing information. No new capturing is done unless
this bit is cleared by writing a 1 to it.
Table 17-26. PCI Express Error Capture Status Register Field Descriptions
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
PCI
PCI Express 2
PCI Express 1
PCI Express 3
USB 1, USB2, or USB3
SATA 1 or SATA 2
Boot sequencer
—
All zeros
Description
Figure
01011
10000
10001
10101
11000
11010
17-27, allows vital error information to be
eSDHC
Processor instruction
Processor data
DMA
eTSEC1 or Security
eTSEC3
24
TO
25
Freescale Semiconductor
26
GSID
Access: Mixed
30
ECV
w1c
31