MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 503

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Context and Operation for GCM-GHASH Cipher Mode
GCM-GHASH denotes the authentication part of GCM cipher mode, and is described in
Section 10.7.1.11.3, “Context for Confidentiality and Data Integrity Cipher
Context and Operation for CMAC (OMAC1) Cipher Mode
CMAC cipher mode is an authentication-only mode of AES. CMAC may be specified using the following
notation:
Using this notation, the specification of CMAC is as follows:
1. Two keys are precomputed as follows:
2. Compute C
3. If |P
Freescale Semiconductor
10. For XCBC-MAC with ICV, check ICCR bits in the status register
1.Notation: {0}
3. Load Key (K if AUX1=0; K1 if AUX1=1)
4. Load Context
5. Set Key size
6. Set data size
7. While available:
8. Write to the end of message register
9. Read MAC from context registers 1-2
•
•
then: MAC = AES-CBC (
else: MAC = AES-CBC (
c.
d. Set AUX2 = 1 if using XCBC-MAC with ICV.
a.
a.
b. K2 = xtime(K1).
E(K,L) denotes the AES-encrypt function;
xtime(L) is defined as follows, where L is a 128-bit vector with L[127] as most significant bit:
— If L[127]=0, then xtime(L)=L<<1 (where ‘<<‘ denotes bitwise left shift)
— Else xtime(L) = (L<<1) XOR 0x87.
n
| = block size (128 bits)
Set AUX1 = 1 if keys K1, K2 and K3 are loaded to key registers 5–6, context registers 7–8 and
9–10, respectively. Otherwise, set AUX1=0, and put K into key registers 1–2, so that keys K1,
K2, and K3 can be computed and written to context registers 5–6, 7–8, and 9–10, respectively.
Load data blocks
K1 = xtime(E (K, {0}
128
n-1
means the bit 0 repeated 128 times
= AES-CBC (P
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
P
P
n
n
128
1
10
, 0, K) ... AES-CBC (P
K1
)).
i
1
, C
K2
n-1
, C
, K)
n-1
, K)
n-1
, C
n-2
, K)
Modes”.
Security Engine (SEC) 3.0
10-73