MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 210

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Value 0
Reset, Clocking, and Initialization
4.5.1.2.4
The eSPI controller configuration is used by the eSPI boot ROM software. After the boot from eSPI has
finished, the user can change this configuration for other uses of the eSPI interface.
The eSPI controller is configured to operate in master mode. The eSPI chip select 0 (SPI_CS[0]) must be
connected to the EEPROM CS and selectively enables the EEPROM.
Figure 4-13
The eSPI controller is configured by the on-chip ROM code. The controller is configured as follows:
Figure 4-14
Field CI0 CP0 REV0 DIV160
The ROM code will initially use the eSPI controller to generate standard read instruction code 0x03
followed by a 3-byte address for every non-sequential read operation (reading from a location which is not
sequential to the last byte read). For sequential read operation, toggling the eSPI clock will cause the eSPI
EEPROM to present the content of the next address location. The serial EEPROM must have an eSPI
compatible interface with read instruction code 0x03 followed by a 2- or 3-byte address.
4-40
•
•
•
•
•
0
Data is shifted out data on SPIMOSI during the falling edge of SPI_CLK. It samples data in from
SPIMISO during the rising edge of SPI_CLK.
The clock is low when the line is idle.
It uses 8-bit length characters.
The platform clock is divided by 256. For example, when the platform clock is configured to
533 MHz, the SPI_CLK will run at 2.08 MHz. (Note that frequency setting can be changed by
using the CF control word, as explained in the
The MSB is sent and received first.
0
1
shows the external signal connection.
shows the default eSPI CS0 mode register (SPMODE0) configuration.
1
2
eSPI Controller Configuration
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
1
3
Figure 4-14. eSPI CS0 Mode Register (SPMODE0) Configuration
MPC8536E
0 0 0 1
4
SPI_CS[0]
SPIMOSI
SPIMISO
SPI_CLK
PM0
Figure 4-13. External Signal Connection
7
ODD0
0
8
0 0
9 10
—
POL0
11
0
V
CC
12
0 1 1 1 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0
“Configuration Words
LEN0
15 16
V
CC
CS0BEF
D (Data In)
Q (Data Out)
C (Serial Clock)
S (Chip Select)
HOLD
19 20
EEPROM
CS0AFT
Section.”
23 24
Freescale Semiconductor
CS0CG
28 29
—
31