MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 696

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Local Bus Controller
strobe negation in write cycles. When this attribute is asserted, the strobe is negated one quarter of a clock
before the normal case. For example, when ACS = 00 and CSNT = 1, LWEn is negated one quarter of a
clock earlier, as shown in
For example, when ACS = 00, CSNT = 1 and TRLX = 0, LWEn is negated one quarter of a clock earlier
and LCSn is negated normally as shown in
13.4.2.3.3
ORx[TRLX] is provided for memory systems that require more relaxed timing between signals. Setting
TRLX = 1 has the following effect on timing:
Figure 13-39
Figure 13-40
13-54
1. LCSn is affected by CSNT and TRLX only if ACS[0] is non zero. However, LWEn is affected
2. When CSNT attribute is asserted, the strobe is negated one quarter of a clock before the normal
3. TRLX = 1 in conjunction with CSNT = 1, negates the LCSn and LWEn 1+1/4 cycle earlier.
•
•
•
•
•
LBCTL
LCLK
LCS n
LWE n
LALE
LAD
LOE
independent of ACS.
case.
An additional bus cycle is added between the address and control signals (but only if ACS is not
equal to 00).
The number of wait states specified by SCY is doubled, providing up to 30 wait states.
The extended hold time on read accesses (EHTR) is extended further.
LCSn signals are negated one cycle earlier during writes (but only if ACS is not equal to 00).
LWE[0:3] signals are negated one cycle earlier during writes.
TA
A
Address
and
also shows address and data multiplexing on LAD for a pair of writes issued consecutively.
Relaxed Timing
Figure 13-40
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
(XACS = 0, ACS = 1x, SCY = 1, CSNT = 0, TRLX = 1, EHTR = 0)
Figure 13-39. GPCM Relaxed Timing Back-to-Back Reads
Figure
ACS = 10
show relaxed timing read and write transactions. The example in
13-38.
SCY = 1, TRLX = 1
ACS = 11
Latched Address
Figure
13-38.
Read Data
extended hold time
Freescale Semiconductor
turnaround
bus
Address