MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1540

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Global Utilities
The PMC allows several wake-up events source to exit low power mode, such as wake on LAN (magic
packet or user defined), USB, GPIO, and internal timer. The wake-up events are mapped to OpenPIC
interrupts to generate a wake-up interrupt to the PMC.
23.5.1.2
The MPC8536E has four low-power states: doze, nap, sleep and deep sleep. The mapping of core and
device power management states is shown in
of the e500 core.
For each operating state represented in the diagram, the cores state is listed first, with the corresponding
state of the MPC8536E shown beneath it in parenthesis. Note that there are many other variables that
control the state transitions between MPC8536E power management states. These additional variables are
described in more detail in
23.5.1.3
CKSTP_IN0/1 are not described here because they are not considered power management signals,
although asserting these do stop the cores and a stopped core is technically in a low-power mode.
CKSTP_IN0/1 are described in
23-48
Relationship Between Core and Device Power Management States
CKSTP_IN0/1 is Not Power Management
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Figure 23-34. e500 Core Power Management State Diagram
Section 23.5.1.8, “Power-Down Sequence Coordination.”
core_stop & core_halt
Section 23.3.2, “Detailed Signal Descriptions.”
¬ core_tben
core_halt
dpslp
Figure 23-34
Core-Powered Off
Core-Stopped
Core-Stopped
(Deep Sleep)
Core-Halted
Full On
(Sleep)
(Doze)
(Nap)
¬ core_halt
¬ core_stop
core_tben
¬dpslp
showing state transitions from the perspective
¬ core_halt
core_halt & ¬ core_stop
core_stop
¬ core_tben
dpslp
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